On-chip surge protection circuit
The present invention provides an on-chip surge protection circuit, including a low voltage rail, a negative transmitter differential output, a positive transmitter differential output, and a surge protection component. The surge protection component includes a first end, a second end, and a control end. The first end is connected to the transmitter differential output N. The second end is connected to the transmitter differential output P. The control end is connected to the low voltage rail.
1. An on-chip surge protection circuit, comprising:
a low voltage rail;
a negative transmitter differential output;
a positive transmitter differential output; and
a surge protection component, the surge protection component including:
a first end connected to the negative transmitter differential output;
a second end connected to the positive transmitter differential output; and
a control end receiving a fixed voltage of the low voltage rail.
2. The on-chip surge protection circuit of claim 1 , the surge protection component is integrated inside a chip.
3. The on-chip surge protection circuit of claim 1 , wherein a surge induces a negative differential surge voltage at the negative transmitter differential output, and induces a positive differential surge voltage at the positive transmitter differential output; the surge protection component being configured to be turned on according to the negative differential surge voltage, the positive differential surge voltage, and the low voltage rail's voltage.
4. The on-chip surge protection circuit of claim 3 , wherein the surge protection component is configured to be turned off when there is no surge or the surge disappears.
5. The on-chip surge protection circuit of claim 1 , wherein the low voltage rail's voltage serves as a surge control signal for the surge protection component.
6. The on-chip surge protection circuit of claim 1 , wherein the surge protection component forms a bypass path between the negative transmitter differential output and the positive transmitter differential output to drain surge current away.
7. The on-chip surge protection circuit of claim 6 , wherein the bypass path is a bidirectional path for the surge current to follow from the negative transmitter differential output to the positive transmitter differential output, or to flow from the positive transmitter differential output to the negative transmitter differential output, according to a negative differential surge voltage and a positive differential surge voltage.
8. The on-chip surge protection circuit of claim 1 , wherein the surge protection component is a bipolar junction transistor (BJT), a silicon controlled rectifier (SCR), a field oxide device (FOD), or a metal-oxide-semiconductor (MOS) field effect transistor.
9. The on-chip surge protection circuit of claim 1 , wherein the surge protection component is a parasitic component.
10. The on-chip surge protection circuit of claim 1 , wherein the surge protection component is formed of an oxide diffusion diode structure or a well diode structure.
11. The on-chip surge protection circuit of claim 1 , further comprising:
a first pull-up component arranged between a high voltage rail and the negative transmitter differential output;
a second pull-up component arranged between the high voltage rail and the positive transmitter differential output;
a first pull-down component arranged between the negative transmitter differential output and the low voltage rail; and
a second pull-down component arranged between the positive transmitter differential output and the low voltage rail.
12. The on-chip surge protection circuit of claim 11 , wherein the first pull-up component, the second pull-up component, the first pull-down component, and/or the second pull-down component is a diode, a silicon controlled rectifier, a bipolar junction transistor, or a metal-oxide-semiconductor field effect transistor.
13. The on-chip surge protection circuit of claim 11 , wherein the first pull-up component, the second pull-up component, the first pull-down component, and/or the second pull-down component is formed by forming a p-well and an n-well in a deep n-well.
14. The on-chip surge protection circuit of claim 11 , wherein the surge protection component is a parasitic component derived from the first pull-up component, the second pull-up component, the first pull-down component, and the second pull-down component.
15. The on-chip surge protection circuit of claim 1 , wherein the on-chip surge protection circuit is configured to withstand a surge voltage of 0 to 4 kV under conditions of open circuit voltage wave 1.2 μs/50 μs, and short circuit current wave 8 μs/20 μs.
16. The on-chip surge protection circuit of claim 1 , wherein the on-chip surge protection circuit is configured to withstand a surge voltage of 0 to 4 kV under conditions of open circuit voltage wave 10 μs/700 μs, and short circuit current wave 5 μs/320 μs.
17. An electronic device, comprising:
a primary-side transformer;
a secondary-side transformer coupled to the primary-side transformer; and
a chip connected to the secondary-side transformer, and including the on-chip surge protection circuit of claim 1 .
18. The electronic device of claim 17 , wherein the electronic device excludes any external resistance, and also excludes any external surge protector.
19. The electronic device of claim 17 , wherein the electronic device is a circuit board or a digital subscriber line.
20. The on-chip surge protection circuit of claim 1 , wherein the fixed voltage is ground.