Configuring first subsystem with a master processor and a second subsystem with a slave processor

1. An apparatus comprising:

a plurality of subsystems comprising a first subsystem and a second subsystem;

a master processor to, in response to power on of the apparatus, execute first instructions to configure the first subsystem and provide second instructions; and

a slave processor to receive the second instructions from the master processor and execute the second instructions to configure the second subsystem, wherein

the first instructions comprise a given first instruction having operands representing a given second instruction of the second instructions; and

the execution of the given first instruction by the master processor causes the master processor to communicate the given second instruction to the slave processor.

2. The apparatus of claim 1 , wherein the execution of the given first Instruction further causes the master processor to:

generate a decode signal to represent selection of the slave processor; and

provide the given first instruction to an instruction bus coupled to the slave processor.

3. The apparatus of claim 1 , wherein the master processor communicates with the first subsystem using a first bus communication protocol, and the slave processor communicates with the second subsystem using a second bus communication protocol different from the first bus communication protocol.

4. The apparatus of claim 1 , wherein the plurality of subsystems further comprises at least one additional subsystem, the apparatus further comprising:

at least one additional slave processor to, in response to the power on of the apparatus, receive and execute instructions from the master processor to configure the at least one additional subsystem.

5. The apparatus of claim 1 , wherein the first subsystem comprises a memory controller, and the second subsystem comprises a memory interface.

6. The apparatus of claim 1 , wherein the plurality of subsystem comprises at least one of

a memory interface, a memory controller, a bus controller or a voltage supply.

7. The apparatus of claim 1 , further comprising:

a general purpose processor to execute bootstrap instructions, wherein the master processor executes the first instructions autonomously with respect to the general purpose processor, while the general purpose processor is held in reset, the slave processor executes the second instructions autonomously with respect to the general purpose processor while the general purpose processor is held in reset, and the general purpose processor executes the bootstrap instructions after being released from reset.

8. The apparatus of claim 1 , further comprising:

a memory to store a plurality of instructions, wherein the plurality of instructions includes the first instructions, a case instruction and groups of instructions associated with the case instruction;

wherein:

a given group of instructions of the groups of instructions corresponds to the first instructions; and

the master processor to, in response to executing the case instruction, selects the first instructions for execution by the master processor based on a vector of data received by the apparatus identifying the given group.

9. The apparatus of claim 7 , wherein:

the apparatus further comprises a root of trust storing an immutable fingerprint; and

the general purpose processor, in response to the first processor being released from reset, validates the bootstrap instructions based on the immutable fingerprint.

10. The apparatus of claim 7 , further comprising a bus multiplexer, wherein the master processor:

controls the bus multiplexer to cause the bus multiplexer to couple the master processor to the first subsystem to configure the first subsystem; and

couples the general purpose processor to the first subsystem to allow the general purpose processor to communicate with the first subsystem when the general purpose processor is released from reset.

11. A computer system comprising:

a plurality of central processing units (CPUs);

a system memory; and

a baseboard management controller comprising:

a plurality of subsystems including a first subsystem and a second subsystem;

at least one processing core to execute instructions to perform system management tasks for the computer system;

a master configurator to, in response to power up of the baseboard management controller, execute instructions to configure the first subsystem and provide second instructions; and

a slave configurator to receive the second instructions and execute the second instructions to configure the second subsystem,

wherein the baseboard management controller is fabricated on a monolithic semiconductor die.

12. The computer system of claim 11 , wherein:

the master configurator executes a first instruction having operands that represent a given second instruction of the second instructions; and

the master configurator, in response to executing the first instruction, communicates the given second instruction to the slave configurator.

13. The computer system of claim 11 , wherein:

the baseboard management controller further comprises a plurality of slave configurators, including the slave configurator that receives and executes the second instructions;

the baseboard management controller further comprises an instruction bus; and

the master configurator, in response to executing the first instruction, generates a decode signal to select the slave configurator that receives and executes the second instructions.

14. The computer system of claim 13 , wherein the master configuration and the plurality of slave configurators are associated with a plurality of different bus communication protocols used to communicate data with the plurality of subsystems.

15. A method comprising:

a general purpose processing core of an embedded processing system executing instructions to boot an embedded processing system;

holding the general purpose processing core in reset, in response to a power on of the embedded processing system; and

while the general purpose processing core is held in reset:

a master processor of the embedded processing system executing first instructions, wherein executing the first instructions configures a first subsystem of the embedded processing system and causes the master processor to communicate second instructions to a slave processor of the embedded processing system; and

the slave processor executing the second instructions to configure the second subsystem.

16. The method of claim 15 , wherein:

the first instructions comprise a given first instruction having operands to encode a given second instruction of the second instructions; and

executing the first instructions comprises the master processor executing the given first instruction, and the execution of the given first instruction by the master processor causes the master processor to communicate the given second instruction to the slave processor.

17. The method of claim 15 , wherein a cryptographic check failure prevents the general purpose processing core from being released from reset, the method further comprising

using at least one of the configured first subsystem and the second configured subsystem to communicate a message representing the cryptographic check failure.

18. The method of claim 15 , further comprising:

storing a plurality of instructions including the first instructions in a memory of the embedded processing system, wherein the plurality of instructions include the first instructions and include groups of instructions associated with the case instruction, and a given group of instructions of the groups of instructions corresponds to the first instructions; and

the master processor executing the case instruction, wherein the master processor executing the case instruction causes the master processor to select the first instructions for execution by the master processor based on vector of data received by the embedded processing system and identifying the given group.