Controlling trap formation to improve memory window in one-time program devices
In some embodiments, the present disclosure relates to a one-time program (OTP) memory cell. The OTP memory cell includes a read transistor and a program transistor neighboring the read transistor. The read transistor includes a read dielectric layer and a read gate electrode overlying the read dielectric layer. The program transistor includes a program dielectric layer and a program gate electrode overlying the program dielectric layer. The program transistor has a smaller breakdown voltage than the read transistor.
1. A method of forming a one-time program (OTP) memory cell, the method comprising:
forming a first dummy gate stack comprising a first dummy gate electrode over a program dielectric layer on a substrate;
forming a second dummy gate stack comprising a second dummy gate electrode over a read dielectric layer on the substrate;
forming a masking structure over the second dummy gate stack;
performing a first etching process to remove the first dummy gate electrode to expose the program dielectric layer;
removing the masking structure;
performing a second etching process to remove the second dummy gate electrode to expose the read dielectric layer, wherein the program dielectric layer is exposed to the second etching process; and
forming a program gate electrode over the program dielectric layer and a read gate electrode over the read dielectric layer.
2. The method of claim 1 , wherein in the first etching process and the second etching process use a same plasma etchant.
3. The method of claim 2 , wherein the program dielectric layer is exposed to the same plasma etchant for a longer time period than the read dielectric layer.
4. The method of claim 1 , wherein before the first etching process, the program dielectric layer has a first average surface roughness, and wherein after the second etching process, the program dielectric layer has a second average surface roughness greater than the first average surface roughness.
5. The method of claim 4 , wherein the method further comprises:
forming an additional masking structure over the read gate electrode;
performing a third etching process to remove the program gate electrode to expose the program dielectric layer;
forming a second program gate electrode over the program dielectric layer, wherein the second program gate electrode comprises a different material than the read gate electrode; and
removing the additional masking structure.
6. The method of claim 5 , wherein after the second program gate electrode is formed on the program dielectric layer, the program dielectric layer has a third average surface roughness greater than the second average surface roughness.
7. A method of forming a one-time program (OTP) memory cell, the method comprising:
forming a first dummy gate stack comprising a first dummy gate over a program dielectric layer on a substrate;
forming a second dummy gate stack comprising a second dummy gate over a read dielectric layer on the substrate;
replacing the first and second dummy gates respectively with a first program gate electrode and a read gate electrode;
performing a first etch into the first program gate electrode, while the read gate electrode is masked, to remove the first program gate electrode and to increase a concentration of traps in the program dielectric layer; and
forming a second program gate electrode overlying the program dielectric layer, wherein the second program gate electrode is a different conductive material than the read gate electrode.
8. The method according to claim 7 , wherein a top of the program dielectric layer and a top of the read dielectric layer respectively have a first average surface roughness and a second average surface roughness, and wherein a difference between the first average surface roughness and the second average surface roughness increases from a beginning of the first etch to an end of the first etch.
9. The method according to claim 7 , wherein the replacing comprises:
a second etch into the program dielectric layer while the read dielectric layer is masked by the second dummy gate.
10. The method according to claim 9 , wherein the replacing further comprises removing the first dummy gate before the second etch.
11. The method according to claim 9 , wherein the second etch increases the concentration of traps in the program dielectric layer relative to a concentration of traps in the read dielectric layer.
12. The method according to claim 7 , wherein the read and program dielectric layers have a common top surface roughness at a beginning of the replacing, and wherein the program dielectric layer has a greater top surface roughness than the read dielectric layer at an end of the replacing.
13. The method according to claim 7 , wherein the forming of the first and second dummy gate stacks comprises:
depositing a dielectric layer overlying the substrate;
depositing a dummy layer overlying the dielectric layer; and
patterning the dummy and dielectric layers respectively into the first dummy gate stack and the second dummy gate stack.
14. A method of forming a one-time program (OTP) memory cell, the method comprising:
forming a first dummy gate stack comprising a first dummy gate over a program dielectric layer on a substrate;
forming a second dummy gate stack comprising a second dummy gate over a read dielectric layer on the substrate; and
replacing the first and second dummy gates respectively with a program gate electrode and a read gate electrode, wherein the replacing comprises:
performing a first etch into the first dummy gate while the second dummy gate is masked to remove the first dummy gate; and
performing a second etch into the program dielectric layer and the second dummy gate, wherein the second etch thins the program dielectric layer and removes the second dummy gate;
wherein the program and read dielectric layers share a common breakdown voltage at a beginning of the replacing, and wherein the program dielectric layer has a lesser breakdown voltage than the read dielectric layer at an end of the replacing.
15. The method according to claim 14 , further comprising:
doping the substrate to from a source/drain region in the substrate, between and bordering the first and second dummy gate stacks.
16. The method according to claim 14 , wherein the first and second etches comprise ion bombardment.
17. The method according to claim 14 , wherein the read and program dielectric layers share a common thickness at the beginning of the replacing, and wherein the program dielectric layer has a lesser thickness than the read dielectric layer at the end of the replacing.
18. The method according to claim 14 , wherein the read and program dielectric layers are formed from a common deposition.
19. The method according to claim 14 , wherein in the first etch and the second etch use a same plasma etchant.
20. The method of claim 19 , wherein the program dielectric layer is exposed to the same plasma etchant for a longer time period than the read dielectric layer.