Split gate power device and its method of fabrication
A split gate power device is disclosed having a trench containing a U-shaped gate that, when biased above a threshold voltage, creates a conductive channel in a p-well. Below the gate is a field plate in the trench, coupled to the source electrode, for spreading the electric field along the trench to improve the breakdown voltage. The top gate poly is initially formed relatively thin so that it can be patterned using non-CMP techniques, such as dry etching or wet etching. As such, the power device can be fabricated in conventional fabs not having CMP capability. In one embodiment, the thin gate has vertical and lateral portions that create conductive vertical and lateral channels in a p-well. In another embodiment, the thin gate has only vertical portions along the trench sidewalls for minimizing surface area and gate capacitance.
1. A trenched power device including a split gate MOSFET comprising:
a semiconductor substrate having a first electrode on its bottom surface;
a drift region of a first conductivity type overlying the substrate;
a well region of a second conductivity type within the drift region;
a source region of the first conductivity type within the well region;
a trench having a vertical sidewall along the well region, the trench terminating in the drift region;
a conductive gate within the trench at least along the well region and insulated from the well region, wherein a portion of the well region abutting the trench is a channel region that is inverted by the gate, and conducts current, when a gate bias is above a threshold voltage;
wherein the gate forms a generally U-shape having a lateral top portion that laterally extends over the well region between the source region and the trench, and having a vertical portion that vertically extends between the source region and the drift region;
a conductive field plate within the trench below and insulated from the gate; and
a second electrode electrically contacting the source region and the well region wherein, when a voltage is applied between the first electrode and the second electrode and the gate is biased above the threshold voltage, a generally lateral current flows across a top section of the well region, below the lateral top portion of the gate, and a generally vertical current flows next to the vertical portion of the gate.
2. The device of claim 1 wherein the field plate is connected to the second electrode.
3. The device of claim 1 wherein a bottom portion of the gate extends between vertical portions of the gate.
4. The device of claim 1 wherein the gate has an open area directly above the field plate.
5. The device of claim 1 wherein a transition part of the gate between the lateral top portion and the vertical portion is rounded.
6. The device of claim 1 further comprising a first region of the first conductivity type abutting a bottom of the trench, wherein the first region has a net dopant concentration that is less than a dopant concentration of the drift region.
7. The device of claim 1 further comprising a first region of the second conductivity type abutting a bottom of the trench.
8. The device of claim 1 wherein the first conductivity type is n-type.
9. The device of claim 1 wherein the first conductivity type is p-type.
10. The device of claim 1 wherein the substrate is of the first conductivity type.
11. The device of claim 1 wherein the substrate is of the second conductivity type.
12. A trenched power device including a split gate MOSFET comprising:
a semiconductor substrate having a first electrode on its bottom surface;
a drift region of a first conductivity type overlying the substrate;
a well region of a second conductivity type within the drift region;
a source region of the first conductivity type within the well region;
a trench having a vertical sidewall along the well region, the trench terminating in the drift region;
a conductive gate within the trench at least along the well region and insulated from the well region, wherein a portion of the well region abutting the trench is a channel region that is inverted by the gate, and conducts current, when a gate bias is above a threshold voltage;
wherein the gate forms opposing vertical portions along sidewalls of the trench that vertically extend between the source region and the drift region;
a conductive field plate within the trench below and insulated from the gate, wherein there is a gap between the opposing vertical portions directly above the field plate, so that the gate is not directly above at least a center of the field plate, wherein no portion of the field plate is between the vertical portions of the gate; and
a second electrode electrically contacting the source region and the well region wherein, when a voltage is applied between the first electrode and the second electrode and the gate is biased above the threshold voltage, a generally vertical current flows next to the vertical portions of the gate.
13. The device of claim 12 wherein the gate has no lateral portions extending over the well region.
14. The device of claim 13 wherein the field plate is connected to the second electrode.
15. The device of claim 13 wherein the first conductivity type is n-type.
16. The device of claim 13 wherein the first conductivity type is p-type.
17. The device of claim 13 wherein the substrate is of the first conductivity type.
18. The device of claim 13 wherein the substrate is of the second conductivity type.
19. A method for forming a trenched power device including a split gate MOSFET comprising:
providing a semiconductor substrate having a first electrode on its bottom surface;
forming a drift region of a first conductivity type overlying the substrate;
forming a well region of a second conductivity type within the drift region;
forming a source region of the first conductivity type within the well region;
forming a trench having a vertical sidewall along the well region, the trench terminating in the drift region;
forming a generally U-shaped conductive gate within the trench at least along the well region and insulated from the well region, and patterning the gate using an etching technique other than CMP, wherein a portion of the well region abutting the trench is a channel region that is inverted by the gate, and conducts current, when a gate bias is above a threshold voltage;
wherein the gate forms at least opposing vertical portions along sidewalls of the trench that vertically extend between the source region and the drift region;
forming a conductive field plate within the trench below and insulated from the gate, wherein the gate has an open area directly above the field plate; and
forming a second electrode electrically contacting the source region and the well region wherein, when a voltage is applied between the first electrode and the second electrode and the gate is biased above the threshold voltage, a generally vertical current flows next to the vertical portions of the gate,
wherein forming the gate comprises forming the gate having a lateral top portion that laterally extends over the well region between the source region and the trench, and having the vertical portions that vertically extend between the source region and the drift region wherein, when a voltage is applied between the first electrode and the second electrode and the gate is biased above the threshold voltage, a generally lateral current flows across a top section of the well region, below the lateral top portion of the gate, and a generally vertical current flows next to the vertical portions of the gate.