IP Library Granted Patent US 11,069,585
Granted Patent B2
US 11,069,585 · App. 16/784,687 · Granted Jul 20, 2021

Semiconductor substrate crack mitigation systems and related methods

Inventor: Michael J. Seddon (Gilbert, AZ)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H01L22/22H01L21/2636H01L23/564
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Quick Facts
Patent No.
US 11,069,585
App. No.
16/784,687
Granted
Jul 20, 2021
Kind
B2
Abstract

Implementations of a method for healing a crack in a semiconductor substrate may include identifying a crack in a semiconductor substrate and heating an area of the semiconductor substrate including the crack until the crack is healed.

Claims (31)

1. A method for healing a crack in a semiconductor substrate, the method comprising: identifying a crack in a semiconductor substrate; heating an area of the semiconductor substrate comprising the crack until the crack is healed; electronically identifying the heated area of the semiconductor substrate, the semiconductor substrate comprising one or more semiconductor die; and excluding the one or more semiconductor die formed in the heated area of the semiconductor substrate from further functional use.

2. The method of claim 1 , wherein the semiconductor substrate comprises silicon carbide.

3. The method of claim 1 , wherein the one or more semiconductor die are formed in at least a portion of the semiconductor substrate.

4. The method of claim 1 , further comprising forming a same crystal orientation of the heated area of the semiconductor substrate as a remainder of the semiconductor substrate through one of controlled cooling, controlled heating, and controlled heating and controlled cooling of the heated area of the semiconductor substrate.

5. The method of claim 1 , further comprising forming a different crystal orientation of the heated area of the semiconductor substrate as a remainder of the semiconductor substrate through one of controlled cooling, controlled heating, and controlled heating and controlled cooling of the heated area of the semiconductor substrate.

6. The method of claim 1 , wherein a laser is used to heat an area of the semiconductor substrate.

7. The method of claim 1 , further comprising electronically identifying the area of the semiconductor substrate comprising the crack and only heating substantially the area of the semiconductor substrate electronically identified.

8. A method for mitigating propagation of a crack in a boule, the method comprising:

identifying a crack in a boule; and

removing a portion of the boule comprising the crack prior to forming any semiconductor substrates from the boule.

9. The method of claim 8 , further comprising:

forming a plurality of semiconductor substrates from the boule, one or more of the plurality of semiconductor substrates lacking a removed portion corresponding with the portion of the boule previously removed;

coupling one of the plurality of semiconductor substrates to a carrier substrate;

completing the processing of the one of the plurality of semiconductor substrates through a plurality of different semiconductor processing operations while coupled to the carrier substrate; and

forming a plurality of semiconductor die therefrom.

10. The method of claim 8 , wherein the boule comprises silicon carbide.

11. The method of claim 8 , wherein removing the portion of the boule comprises etching the portion of the boule.

12. The method of claim 8 , wherein removing the portion of the boule comprises polishing a sidewall of the boule.

13. The method of claim 9 , further comprising electronically identifying the removed portion of the one of the plurality of semiconductor substrates on a wafer map associated with the one of the plurality of semiconductor substrates and electronically excluding the removed portion of the one of the plurality of semiconductor substrates from the wafer map prior to subsequent processing.

14. A method for healing a crack in a boule, the method comprising:

identifying a crack in a boule;

heating an area of the boule comprising the crack until the crack is modified to reduce a risk of propagation of the crack to a desired level.

15. The method of claim 14 , wherein the boule comprises silicon carbide.

16. The method of claim 14 , further comprising electronically identifying the heated area of the boule, processing of the boule, and forming a plurality of semiconductor substrates from the boule.

17. The method of claim 16 , further comprising forming a same crystal orientation of the heated area of the boule as a remainder of the boule through one of controlled cooling, controlled heating, and controlled cooling and controlled heating of the heated area of the boule.

18. The method of claim 14 , further comprising forming a different crystal orientation of the heated area of the boule as a remainder of the boule through one of controlled cooling, controlled heating, and controlled heating and controlled cooling of the heated area of the boule.

19. The method of claim 14 , further comprising electronically identifying the area of the boule comprising the crack and only heating the area of the boule electronically identified.

20. The method of claim 16 , further comprising:

forming a plurality of semiconductor die on one of the plurality of semiconductor substrates;

electronically identifying the heated area of the one of the plurality of semiconductor substrates; and

excluding one or more of the plurality of semiconductor die formed in the heated area of the one of the plurality of semiconductor substrates from further functional use.

Assignments (4)
SECURITY INTEREST Recorded Jul 13, 2023
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; GTAT CORPORATION
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064271/0971 →
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 052656, FRAME 0842 Recorded Jun 23, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064080/0149 →
SECURITY INTEREST Recorded May 13, 2020
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 052656/0842 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 7, 2020
From: SEDDON, MICHAEL J.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 051751/0758 →
Continuity (2)
Continuation 15964484 · Apr 27, 2018
Related Publication 20200176336A1 · Jun 4, 2020