Semiconductor device

1. A semiconductor device comprising:

a first transistor; and

a second transistor,

the first transistor and the second transistor being formed in a same active region defined by an element isolation region,

wherein

the active region includes a body region in which the first transistor and the second transistor are formed, a connection portion to which a potential of the body region is connected, and a lead portion that connects the body region and the connection portion,

each of the first transistor and the second transistor formed in the body region includes a channel region, a gate electrode formed on the channel region via a gate insulation film, and a source region and a drain region formed with the channel region interposed therebetween,

the source regions or the drain regions of the first transistor and the second transistor are formed in a common region and have a same potential,

in each of the first transistor and the second transistor, the channel region, the connection portion, and the lead portion have the same conductivity type,

each of the lead portions extends from a corresponding one of the channel regions of the first transistor and the second transistor in a direction perpendicular to a channel direction such that the lead portions are isolated from each other, and each of the gate electrodes extends on a corresponding one of the lead portions,

a width of each of the lead portions is narrower than a distance between corresponding ones of contact portions of the source regions and the drain regions of the first transistor and the second transistor, and

a width of each of the connection portions is equal to or narrower than a gate width of a corresponding one of the gate electrodes extending on the lead portions.

2. The semiconductor device of claim 1 , wherein

the gate width of each of the gate electrodes extending on the lead portions is equal to or narrower than a width enlarged by an amount corresponding to a width of mask displacement width of the gate electrode with respect to the corresponding lead portion.

3. The semiconductor device of claim 1 , wherein

the width of the connection portions and the width of the lead portions are same.

4. The semiconductor device of claim 1 , wherein

each of the lead portions of the first transistor and the second transistor extends from a corresponding one of the channel regions in a same direction.

5. The semiconductor device of claim 1 , wherein

the active region is formed of a semiconductor layer on an insulation layer formed on a substrate.

6. The semiconductor device of claim 1 , wherein

the first transistor and the second transistor are formed of transistors of a same channel type.

7. The semiconductor device of claim 1 , wherein

the width of the gate electrodes formed on the channel regions and the width of the gate electrodes extending on the lead portions are same.

8. The semiconductor device of claim 1 , wherein

the active region further includes a second body region in which a third transistor is formed, a second connection portion to which a potential of the second body region is connected, and a second lead portion that connects the second body region and the second connection portion,

the second lead portion extends from the channel region of the third transistor in an opposite direction to the lead portion of the first transistor or the second transistor, and

the second connection portion is formed with the connection portion of the first transistor or the second transistor in a common region and the second connection portion and the connection portion have a same potential.

9. The semiconductor device of claim 1 , wherein

in each of the channel regions of the first transistor and the second transistors, a third lead portion extends from an opposite side to a side from which the lead portions extend, and

the gate electrodes extending on the lead portions and the gate electrode extending on the third lead portion have a same shape.

10. The semiconductor device of claim 9 , wherein

a third connection portion to which the potential of the body region is connected is further connected to the third lead portion.

11. The semiconductor device of claim 1 , wherein

when the width of the gate electrodes formed on the channel regions and the width of the gate electrodes extending on the lead portions are different and a boundary between each of the gate electrodes formed on the channel regions and a corresponding one of the gate electrode extending on the lead portions is positioned in an outer side than a boundary of the body region in which the first transistor and the second transistor are formed, the gate electrodes formed on the channel regions are perpendicular to the boundary of the body region.

12. The semiconductor device of claim 1 , wherein

when the width of the gate electrodes formed on the channel regions and the width of the gate electrodes extending on the lead portions are different and a boundary between each of the gate electrodes formed on the channel regions and a corresponding one of the gate electrodes extending on the lead portions is positioned in an inner side than a boundary of the body region in which the first transistor and the second transistor are formed, a boundary of each of the gate electrodes formed on the channel regions and a corresponding one of the gate electrodes extending on the lead portions is tilted by an angle of 135 degrees or more.

13. The semiconductor device of claim 1 , wherein

a first transistor group formed in the active region includes a source region and a drain region and is configured such that transistors including the first transistor connected to a first gate and the second transistor connected to a second gate between the source region and the drain region are connected in series from a source region side.

14. The semiconductor device of claim 1 , wherein

a first transistor group formed in the active region includes a source region and a drain region and is configured such that transistors including the first transistor connected to a first gate and the second transistor connected to a second gate between the source region and the drain region are connected in series from a source region side, and

a second transistor group formed in the active region includes a source region that shares a same node with the source region and a drain region that shares a same node with the drain region and is configured such that transistors including a third transistor connected to the first gate and a fourth transistor connected to the second gate between the source region and the drain region are connected in series from a source region side.

15. A semiconductor device,

wherein

a first transistor group formed in an active region includes a source region and a drain region and is configured such that transistors including a first transistor connected to a first gate and a second transistor connected to a second gate between the source region and the drain region are connected in series from a source region side,

in each of the first transistor and the second transistor, the channel region, the connection portion, and the lead portion have the same conductivity type, and

each of respective channel potentials of the first transistor and the second transistor is led out from an active region of a lower layer of the gates.

16. A semiconductor device,

wherein

a first transistor group formed in an active region includes a source region and a drain region and is configured such that transistors including a first transistor connected to a first gate and a second transistor connected to a second gate between the source region and the drain region are connected in series from a source region side,

in each of the first transistor and the second transistor, the channel region, the connection portion, and the lead portion have the same conductivity type, and

a second transistor group formed in the active region includes a source region that shares a same node with the source region and a drain region that shares a same node with the drain region and is configured such that transistors including a third transistor connected to the first gate and a fourth transistor connected to the second gate between the source region and the drain region are connected in series from a source region side, and each of respective channel potentials of the first transistor and the second transistor is led out from an active region of a lower layer of the gates.