IP Library › Granted Patent US 12,021,112
Granted Patent B2
US 12,021,112 · App. 16/785,478 · Granted Jun 25, 2024

Device including first and second capacitors and a storage capacitor

Inventors: Sun-Ja Kwon (Gunpo-si, KR); Jae-Yong Lee (Yongin-si, KR); Ji-Eun Lee (Seoul, KR); So-Young Kang (Gwangju, KR); Sang-Ho Seo (Cheonan-si, KR)
Assignee: Samsung Display Co., Ltd.
H10K59/131H01L27/1222H01L27/1225H01L27/124H01L27/1255H10K59/124
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Quick Facts
Patent No.
US 12,021,112
App. No.
16/785,478
Granted
Jun 25, 2024
Kind
B2
Abstract

An organic light-emitting diode (OLED) display is disclosed. In one aspect, the display includes a substrate and an active pattern formed over the substrate and including first to fourth regions. A gate insulation layer is formed over the active pattern and the substrate, and a first gate electrode is formed over the gate insulation layer and partially overlapping the active pattern. The first gate electrode, the first region and the second region define a first transistor. A second gate electrode is formed on the same layer as the first gate electrode. The second gate electrode, the third region and the fourth region define a second transistor, and the second gate electrode, the second region and the fourth region define a third transistor. A first insulating interlayer is formed over the first gate electrode, the second gate electrode, and the gate insulation layer.

Claims (34)

1. A display device comprising:

a substrate;

a first active pattern disposed on the substrate, the first active pattern including a first region, a second region, a third region, and a fourth region;

a first lower gate electrode disposed on the first active pattern, the first lower gate electrode defining a first transistor together with the first and second regions by partially overlapping the first active pattern;

a first gate electrode spaced apart from the first lower gate electrode on a same layer, the first gate electrode defining a second transistor together with the third and fourth regions and defining a third transistor together with the fourth and second regions by partially overlapping the first active pattern;

a first-first conductive pattern disposed on the first gate electrode and the first lower gate electrode, the first-first conductive pattern defining a first capacitor together with the fourth region by partially overlapping the first active pattern in a thickness direction of the substrate, the first gate electrode being entirely offset from the first-first conductive pattern in a direction perpendicular to the thickness direction of the substrate, the first-first conductive pattern corresponding to the fourth region do not overlap any gate electrode in the thickness direction of the substrate;

a second-first conductive pattern spaced apart from the first-first conductive pattern on a same layer, the second-first conductive pattern defining a second capacitor together with the third region by partially overlapping the first active pattern in the thickness direction of the substrate;

a second conductive pattern spaced apart from the first-first and second-first conductive patterns on a same layer, the second conductive pattern defining a storage capacitor together with the first lower gate electrode by partially overlapping the first lower gate electrode; and

a first light-emitting layer disposed on the first-first and second-first conductive patterns and the second conductive pattern.

2. The display device of claim 1 , further comprising:

a first power supply voltage line overlapping the second-first conductive pattern, the first power supply voltage line being connected to the second-first conductive pattern through a first contact hole, the first power supply voltage line providing a first power supply voltage to the second-first conductive pattern; and

a second power supply voltage line overlapping the first-first conductive pattern, the second power supply voltage line being connected to the first-first conductive pattern through a second contact hole, the second power supply voltage line providing the first power supply voltage to the first-first conductive pattern.

3. The display device of claim 2 , wherein the first power supply voltage line overlaps the first active pattern.

4. The display device of claim 3 , further comprising:

a first data line spaced apart from the first power supply voltage line,

wherein the first data line and the first power supply voltage line are disposed on a same layer.

5. The display device of claim 2 , further comprising:

a second active pattern spaced apart from the first active pattern on a same layer, the second active pattern including a sub-first region, a sub-second region, a sub-third region, and a sub-fourth region; and

a second lower gate electrode disposed on the second active pattern, and defining a sub-first transistor together with the sub-first and sub-second regions by partially overlapping the second active pattern.

6. The display device of claim 5 , wherein a shape of the second active pattern is a substantially same as a shape of the first active pattern, and the second active pattern is spaced apart from the first active pattern in a first direction.

7. The display device of claim 5 , wherein:

the first gate electrode extends in a first direction to overlap the second active pattern, and the first gate electrode defines a sub-second transistor together with the sub-third and sub-fourth regions and defines a sub-third transistor together with the sub-fourth and sub-second regions by partially overlapping the second active pattern; and

the second conductive pattern extends in the first direction to overlap the second active pattern, and defines a sub-storage capacitor together with the second lower gate electrode by partially overlapping the second lower gate electrode.

8. The display device of claim 5 , wherein the first-first conductive pattern extends in a first direction to overlap the second active pattern, and defines a sub-second capacitor together with the sub-third region by partially overlapping the second active pattern.

9. The display device of claim 8 , wherein a first portion of the first-first conductive pattern overlaps a portion of the first active pattern, and a second portion of the first-first conductive pattern overlaps a portion of the second active pattern.

10. The display device of claim 9 , further comprising:

a third-first conductive pattern spaced apart from the first-first conductive pattern on a same layer, the third-first conductive pattern defining a sub-first capacitor together with the sub-fourth region by partially overlapping the second active pattern.

11. The display device of claim 10 , wherein the second-first conductive pattern, the first-first conductive pattern, and the third-first conductive pattern are sequentially arranged on the first and second active patterns in the first direction.

12. The display device of claim 10 , further comprising:

a second light-emitting layer disposed on the first-first and third-first conductive patterns and the second conductive pattern.

13. The display device of claim 5 , wherein the second power supply voltage line overlaps the second active pattern.

14. The display device of claim 13 , further comprising:

a second data line spaced apart from the second power supply voltage line,

wherein the second data line and the second power supply voltage line are disposed on a same layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 1, 2022
From: KWON, SUN-JA; LEE, JAE-YONG; LEE, JI-EUN; KANG, SO-YOUNG; SEO, SANG-HO
To: SAMSUNG DISPLAY CO., LTD.
Reel/Frame 061614/0179 →
Priority Claims (1)
KR 10-2015-0028724 · Feb 28, 2015 · national
Continuity (3)
Continuation 15461387 · Jun 16, 2017
Continuation 14869591 · Sep 29, 2015
Related Publication 20200176548A1 · Jun 4, 2020
Cited By (1)
US 12,740,273