Non-planar semiconductor device having hybrid geometry-based active region
Non-planar semiconductor devices having hybrid geometry-based active regions are described. For example, a semiconductor device includes a hybrid channel region including a nanowire portion disposed above an omega-FET portion disposed above a fin-FET portion. A gate stack is disposed on exposed surfaces of the hybrid channel region. The gate stack includes a gate dielectric layer and a gate electrode disposed on the gate dielectric layer. Source and drain regions are disposed on either side of the hybrid channel region.
1. An integrated circuit structure, comprising:
a channel structure, comprising:
a first nanowire above and spaced apart from a second nanowire, the second nanowire above and spaced apart from a third nanowire, the third nanowire directly on a semiconductor layer above a substrate, wherein the first nanowire, the second nanowire and the third nanowire consist essentially of a first semiconductor material, and wherein the semiconductor layer consists essentially of a second semiconductor material different than the first semiconductor material, and wherein the semiconductor layer has a lateral width less than a lateral width of each of the first nanowire, the second nanowire and the third nanowire;
a gate stack on exposed surfaces of the channel structure; and
source and drain regions on either side of the channel structure.
2. The integrated circuit structure of claim 1 , wherein the first semiconductor material is silicon, and the second semiconductor material is silicon germanium.
3. The integrated circuit structure of claim 1 , wherein the semiconductor layer of the channel structure is continuous with the substrate.
4. The integrated circuit structure of claim 3 , wherein the gate stack is isolated from the substrate by a bottom gate isolation (BGI) structure.
5. The integrated circuit structure of claim 1 , wherein the gate stack comprises a gate dielectric layer, and a gate electrode on the gate dielectric layer.
6. An integrated circuit structure, comprising:
a hybrid channel region comprising a multi-wire portion above an omega-FET portion, the omega-FET portion having a wider portion on a narrower portion, wherein the multi-wire portion and the wider portion of the omega-FET portion consist essentially of a first semiconductor material, and wherein the narrower portion of the omega-FET portion comprises a second semiconductor material different than the first semiconductor material;
a gate stack on exposed surfaces of the hybrid channel region; and
source and drain regions on either side of the hybrid channel region.
7. The integrated circuit structure of claim 6 , wherein the first semiconductor material is silicon, and the second semiconductor material is silicon germanium.
8. The integrated circuit structure of claim 6 , wherein the omega-FET portion of the hybrid channel region is continuous with a bulk semiconductor substrate.
9. The integrated circuit structure of claim 8 , wherein the gate stack is isolated from the bulk semiconductor substrate by a bottom gate isolation (BGI) structure.
10. The integrated circuit structure of claim 6 , wherein the gate stack comprises a gate dielectric layer, and a gate electrode on the gate dielectric layer.
11. A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a channel structure comprising a first nanowire above and spaced apart from a second nanowire, the second nanowire above and spaced apart from a third nanowire, the third nanowire directly on a semiconductor layer above a substrate, wherein the first nanowire, the second nanowire and the third nanowire consist essentially of a first semiconductor material, and wherein the semiconductor layer consists essentially of a second semiconductor material different than the first semiconductor material, and wherein the semiconductor layer has a lateral width less than a lateral width of each of the first nanowire, the second nanowire and the third nanowire;
a gate stack on exposed surfaces of the channel structure; and
source and drain regions on either side of the channel structure.
12. The computing device of claim 11 , further comprising:
a memory coupled to the board.
13. The computing device of claim 11 , further comprising:
a communication chip coupled to the board.
14. The computing device of claim 11 , further comprising:
a camera coupled to the board.
15. The computing device of claim 11 , further comprising:
a battery coupled to the board.
16. The computing device of claim 11 , further comprising:
an antenna coupled to the board.
17. The computing device of claim 11 , wherein the component is a packaged integrated circuit die.
18. The computing device of claim 11 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.
19. The computing device of claim 11 , wherein the computing device is selected from the group consisting of a mobile phone, a laptop, a desk top computer, a server, and a set-top box.
20. The computing device of claim 11 , wherein the semiconductor layer of the channel structure is continuous with the semiconductor substrate.