Memory with FRAM and SRAM of IC and method for accessing memory
Memories are provided. A memory includes a plurality of ferroelectric random access memory (FRAM) cells arranged in a first memory array, and a plurality of static random access memory (SRAM) cells arranged in a second memory array. There are more FRAM cells than SRAM cells. The first memory array and the second memory array share the same bus.
1. A memory, comprising:
a plurality of ferroelectric random access memory (FRAM) cells arranged in a first memory array; and
a plurality of static random access memory (SRAM) cells arranged in a second memory array,
wherein number of the FRAM cells is greater than that of the SRAM cells,
wherein the first memory array and the second memory array share the same bus, and the first memory array and the second memory array are accessed with different rates through the same bus.
2. The memory as claimed in claim 1 , wherein size of each of the SRAM cells is greater than that of each of the FRAM cell.
3. The memory as claimed in claim 1 , wherein the number of transistors of each of the SRAM cells is greater than that of each of the FRAM cells.
4. The memory as claimed in claim 1 , wherein each of the FRAM cells comprises a transistor and a ferroelectric capacitor, and the transistor is a FinFET.
5. The memory as claimed in claim 1 , wherein each of the FRAM cells comprises a ferroelectric field-effect transistor (FeFET).
6. The memory as claimed in claim 5 , wherein a gate structure of the FeFET comprises:
an interfacial layer over a channel of the FeFET;
a ferroelectric layer over the interfacial layer; and
a gate electrode over the ferroelectric layer.
7. The memory as claimed in claim 5 , wherein a gate structure of the FeFET comprises:
an interfacial layer over a channel of the FeFET;
a dielectric layer of high-K material over the interfacial layer;
a gate electrode over the dielectric layer; and
a ferroelectric layer over the gate electrode.
8. The memory as claimed in claim 7 , wherein the gate structure of the FeFET further comprises:
a metal layer between the gate electrode and the ferroelectric layer.
9. The memory as claimed in claim 1 , wherein the first memory array is accessed with a lower write rate and the second memory array is accessed with a higher write rate through the same bus.
10. An integrated circuit (IC), comprising:
a memory, comprising:
a first memory array formed by a plurality of ferroelectric random access memory (FRAM) cells; and
a second memory array formed by a plurality of static random access memory (SRAM) cells; and
a controller configured to access the memory according to at least one write instruction,
wherein when a write rate is greater than a predetermined rate, the controller is configured to access the second memory array through a bus according to the write instruction,
wherein when the write rate is less than or equal to the predetermined rate, the controller is configured to access the first memory array through the same bus according to the write instruction.
11. The IC as claimed in claim 10 , wherein the number of the FRAM cells is greater than that of the SRAM cells, and size of the SRAM cell is greater than that of the FRAM cell.
12. The IC as claimed in claim 10 , wherein number of transistors of the SRAM cell is greater than that of the FRAM cell.
13. The IC as claimed in claim 10 , wherein the SRAM cell comprises two P-type transistors and four N-type transistors, and the N-type and P-type transistors are fin field effect transistors (FinFETs).
14. The IC as claimed in claim 10 , wherein the FRAM cell comprises a transistor and a ferroelectric capacitor, and the transistor is a FinFET.
15. The IC as claimed in claim 10 , wherein the FRAM cell comprises a ferroelectric field-effect transistor (FeFET).
16. A method for accessing a memory, wherein the memory comprises a first memory array formed by a plurality of ferroelectric random access memory (FRAM) cells, and a second memory array formed by a plurality of static random access memory (SRAM) cells, the method comprising:
in response to at least one write instruction, accessing the first memory array through a bus when a write rate is less than or equal to a predetermined rate; and
in response to the write instruction, accessing the second memory array through the bus when the write rate is greater than the predetermined rate,
wherein the write rate represents the number of write instructions that the memory executes in a predetermined period of time.
17. The method as claimed in claim 16 , wherein number of the FRAM cells is greater than that of the SRAM cells, and size of the SRAM cell is greater than that of the FRAM cell.
18. The method as claimed in claim 16 , wherein the SRAM cell comprises two P-type transistors and four N-type transistors, and the N-type and P-type transistors are fin field effect transistors (FinFETs).
19. The method as claimed in claim 16 , wherein the FRAM cell comprises a transistor and a ferroelectric capacitor, and the transistor is a FinFET.
20. The method as claimed in claim 16 , wherein the FRAM cell comprises a ferroelectric field-effect transistor (FeFET).