Apparatuses and methods for tunable digital power amplifiers
Embodiments of the disclosure are drawn to apparatuses and methods for a tunable digital power amplifier (DPA). The tunable DPA may be coupled to a reconfigurable capacitor to form a frequency tunable DPA. The capacitance of the reconfigurable capacitor may be adjusted to optimize the DPA to operate at a desired frequency band. The single tunable DPA may operate over a wide range of frequencies.
1. An apparatus, comprising:
a digital power amplifier, wherein the digital power amplifier includes a switched capacitor power amplifier (SCPA) including a unary capacitor array and a binary capacitor array, wherein capacitors of the binary capacitor array are configured to receive least significant bits of a signal and capacitors of the unary array are configured to receive most significant bits of the signal; and
a reconfigurable capacitor coupled in series with the digital power amplifier, wherein the reconfigurable capacitor is configured to tune a resonant frequency of the digital power amplifier.
2. The apparatus of claim 1 , wherein the reconfigurable capacitor includes an array of capacitors.
3. The apparatus of claim 1 , wherein the unary capacitor array and the binary capacitor array are coupled in parallel.
4. The apparatus of claim 1 , wherein the SCPA includes a switch configured to selectively activate a capacitor of the SCPA.
5. The apparatus of claim 4 , wherein the switch includes a cascoded inverter.
6. The apparatus of claim 4 , further comprising a control logic circuit configured to control the switch.
7. The apparatus of claim 1 , further comprising a matching network coupled in series with the reconfigurable capacitor, wherein the matching network is configured to couple the apparatus to an antenna.
8. The apparatus of claim 7 , wherein the matching network includes an LC balun.
9. The apparatus of claim 7 , wherein the matching network includes an inductor and a resistance.
10. The apparatus of claim 1 , further comprising an inductor coupled between the digital power amplifier and the reconfigurable capacitor.
11. An apparatus comprising:
a digital power amplifier;
a reconfigurable capacitor coupled in series with the digital power amplifier, wherein the reconfigurable capacitor is configured to tune a resonant frequency of the digital power amplifier;
a vector signal generator configured to generate a phase modulated signal; and
a clock circuit configured to provide a modulated clock signal, based at least in part on the phase modulated signal, to the digital power amplifier.
12. An apparatus comprising:
a digital power amplifier;
a reconfigurable capacitor coupled in series with the digital power amplifier, wherein the reconfigurable capacitor is configured to tune a resonant frequency of the digital power amplifier; and
a binary-to-thermometer circuit configured to provide most significant bits of a signal to the digital power amplifier and a re-timing circuit configured to provide least significant bits of the signal to the digital power amplifier.
13. A method for designing an output stage of a switched capacitor array power amplifier (SCPA), the method comprising:
selecting a value for a resistance;
calculate an output power as a function of a channel width of an NMOS device and a channel width of a PMOS device;
compare the output power to a desired output power; and
if the output power meets a specification for the desired output power, calculate the channel width of the NMOS device and the channel width of the PMOS device that maximizes a total efficiency of the SCPA; or
if the output power does not meet the specification for the desired output power, adjust the value of the resistance.
14. The method of claim 13 , further comprising repeating the method of claim 13 until the output power meets the specification for the desired output power.
15. The method of claim 13 , wherein meeting the specification for the desired output power comprises the output power is equal to or greater than the desired output power.
16. The method of claim 13 , wherein adjusting the value of the resistance comprises reducing the value.