Memory storage device having automatic error repair mechanism and method thereof

1. A memory storage device comprising:

a connection interface configured to receive a write or read command and a word line address associated with the write or read command;

a memory array comprising a memory bank which comprises an error correction code (ECC) detector, a plurality of memory cells controlled by the word line address, and a plurality of redundant memory cells controlled by a redundant word line address;

a fuse blowing controller configured to receive the word line address to blow an electrical fuse of the word line address to enable the plurality of redundant memory cells; and

a memory control circuit coupled to the connection interface, the memory array and the fuse blowing controller and configured to:

perform a write or read operation to the plurality of memory cells in response to receiving the write or read command;

receive a failure indication from the ECC detector in response to detecting an error from the write or read operation;

blow the electrical fuse of the word line address to enable the plurality of redundant memory cells in response to receiving the failure indication; and

automatically transfer data from the plurality of memory cells through a bit line into the plurality of redundant memory cells in response to the electrical fuse having been blown.

2. The memory storage device of claim 1 , wherein transfer the data from the plurality of memory cells through the bit line into the plurality of redundant memory cells comprising:

detect an auto-refresh command; and

transfer data from the plurality of memory cells through the bit line into the plurality of redundant memory cells by copying the data from a sense amplifier into the plurality of redundant memory cells.

3. The memory storage device of claim 2 , wherein transfer the data from the plurality of memory cells through the bit line into the plurality of redundant memory cells further comprising:

transfer the data from the plurality of memory cells through the bit line into the plurality of redundant memory cells without transferring the data through a data line.

4. The memory storage device of claim 1 , wherein the ECC detector is configured to:

perform an ECC check;

repair data associated with the word line address in response to failing the ECC check; and

transmit the failure indication to the memory control circuit in response to failing to repair the data.

5. The memory storage device of claim 4 , wherein transmit the failure indication to the memory control circuit in response to failing to repair the data comprising:

transmit to the memory control circuit the word line address and an ECC failure flag in response to failing to repair the data.

6. The memory storage device of claim 5 , wherein the fuse blowing controller is further configure to:

transmit a fuse blowing flag which indicates that blowing the electrical fuse of the word line address has been complete.

7. The memory storage device of claim 6 , wherein the memory control circuit is further configured to:

wait for an auto-refresh command or a self-refresh command in response to receiving the fusing blowing flag and the ECC failure flag.

8. The memory storage device of claim 7 , wherein the memory control circuit is further configured to:

refresh the plurality of redundant memory cells in response to receiving the auto-refresh command or the self-refresh command.

9. The memory storage device of claim 5 , wherein the memory control circuit further comprising:

a refresh address latch configured to receive the ECC failure flag and the word line address for performing a refresh operation of the plurality of redundant memory cells.

10. The memory storage device of claim 1 , wherein the plurality of redundant memory cells and the plurality of memory cells have the same row address.

11. An automatic error repair method used by a memory storage device, the method comprising:

receiving a write or read command and a word line address associated with the write or read command;

performing a write or read operation to a plurality of memory cells controlled by the word line address of a memory array in response to receiving the write or read command, wherein the memory array comprising a memory bank which comprises an error correction code (ECC) detector, the plurality of memory cells, and a plurality of redundant memory cells controlled by a redundant word line address;

receiving a failure indication from the ECC detector in response to detecting an error from the write or read operation;

blowing an electrical fuse of the word line address to enable the plurality of redundant memory cells in response to receiving the failure indication; and

automatically transferring data from the plurality of memory cells through a bit line into the plurality of redundant memory cells in response to the electrical fuse having been blown.

12. The method of claim 11 , wherein transferring the data from the plurality of memory cells through the bit line into the plurality of redundant memory cells comprising:

detecting an auto-refresh command; and

transferring data from the plurality of memory cells through the bit line into the plurality of redundant memory cells by copying the data from a sense amplifier into the plurality of redundant memory cells.

13. The method of claim 12 , wherein transferring the data from the plurality of memory cells through the bit line into the plurality of redundant memory cells further comprising:

transferring the data from the plurality of memory cells through the bit line into the plurality of redundant memory cells without transferring the data through a data line.

14. The method of claim 11 , wherein receiving the failure indication from the ECC detector further comprising:

performing an ECC check;

repairing the data associated with the word line address in response to failing the ECC check; and

receiving the failure indication from the ECC detector in response to failing to repair the data.

15. The method of claim 14 , wherein receiving the failure indication from the ECC detector in response to failing to repair the data comprising:

receiving the word line address and an ECC failure flag in response to failing to repair the data.

16. The method of claim 15 further comprising:

receiving a fuse blowing flag which indicates that blowing the electrical fuse of the word line address has been complete.

17. The method of claim 16 further comprising:

waiting for an auto-refresh command or a self-refresh command in response to receiving the fusing blowing flag and the ECC failure flag.

18. The method of claim 17 further comprising:

refreshing the plurality of redundant memory cells in response to receiving the auto-refresh command or the self-refresh command.

19. The method of claim 15 further comprising:

receiving the ECC failure flag and the word line address for performing a copy operation during a refresh period of the plurality of redundant memory cells.

20. The method of claim 11 , wherein the plurality of redundant memory cells and the plurality of memory cells have the same row address.