Logic drive with brain-like elasticity and integrality based on standard commodity FPGA IC chips using non-volatile memory cells
A chip package comprises an interposer; an FPGA IC chip over the interposer, wherein the FPGA IC chip comprises a programmable logic block configured to perform a logic operation on its inputs, wherein the programmable logic block comprises a look-up table configured to be provided with multiple resulting values of the logic operation on multiple combinations of the inputs of the programmable logic block respectively, wherein the programmable logic block is configured to select, in accordance with one of the combinations of its inputs, one from the resulting values into its output, and multiple non-volatile memory cells configured to save the resulting values respectively; multiple first metal bumps between the interposer and the FPGA IC chip; and an underfill between the interposer and the FPGA IC chip, wherein the underfill encloses the first metal bumps.
1. A chip package comprising:
an interposer comprising a silicon substrate, a plurality of metal vias passing through the silicon substrate, a first interconnection metal layer over the silicon substrate, a second interconnection metal layer over the silicon substrate and the first interconnection metal layer, and an insulating dielectric layer over the silicon substrate and between the first and second interconnection metal layers, and
a first semiconductor integrated-circuit (IC) chip over the interposer, wherein the first semiconductor integrated-circuit (IC) chip couples to the interposer, wherein the first semiconductor integrated-circuit (IC) chip comprises a non-volatile memory cell for use to store a resulting value of a look-up table (LUT) for a logic operation, wherein the non-volatile memory cell comprises a first magnetoresistive-random-access-memory (MRAM) cell, and a selection circuit comprising a first set of input points for a first input data set for the logic operation and a second set of input points for a second input data set, wherein the second input data set comprises a first data associated with the resulting value stored in the non-volatile memory cell, wherein the selection circuit is configured to select, in accordance with the first input data set, the first data from the second input data set as an output data for the logic operation.
2. The chip package of claim 1 , wherein the non-volatile memory cell further comprises a second magnetoresistive-random-access-memory (MRAM) cell coupling to the first magnetoresistive-random-access-memory (MRAM) cell.
3. The chip package of claim 1 , wherein the non-volatile memory cell further comprises a resistor coupling to the first magnetoresistive-random-access-memory (MRAM) cell.
4. The chip package of claim 1 , wherein the first magnetoresistive-random-access-memory (MRAM) cell comprises first and second magnetic layers and an oxide layer between the first and second magnetic layers.
5. The chip package of claim 4 , wherein the oxide layer comprises magnesium oxide.
6. The chip package of claim 4 , wherein the first magnetic layer comprises cobalt (Co), iron (Fe) and boron (B).
7. The chip package of claim 4 , wherein the first magnetoresistive-random-access-memory (MRAM) cell further comprises an antiferromagnetic layer, wherein the first magnetic layer is between the oxide layer and the antiferromagnetic layer.
8. The chip package of claim 1 , wherein the first semiconductor integrated-circuit (IC) chip of the chip package is a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip.
9. The chip package of claim 1 further comprising a digital-signal-processing (DSP) chip over the interposer and on a same plane as the first semiconductor integrated-circuit (IC) chip, wherein the digital-signal-processing (DSP) chip couples to the interposer.
10. The chip package of claim 1 further comprising a central-processing-unit (CPU) chip over the interposer and on a same plane as the first semiconductor integrated-circuit (IC) chip, wherein the central-processing-unit (CPU) chip couples to the interposer.
11. The chip package of claim 1 further comprising a graphical-processing-unit (GPU) chip over the interposer and on a same plane as the first semiconductor integrated-circuit (IC) chip, wherein the graphical-processing-unit (GPU) chip couples to the interposer.
12. The chip package of claim 1 further comprising a second semiconductor integrated-circuit (IC) chip over the interposer and on a same plane as the first semiconductor integrated-circuit (IC) chip, wherein the second semiconductor integrated-circuit (IC) chip couples to the interposer.
13. The chip package of claim 1 further comprising a plurality of metal bumps at a bottom of the interposer, wherein the plurality of metal bumps couple to the plurality of metal vias respectively.
14. The chip package of claim 1 further comprising a plurality of metal bumps between the interposer and the first semiconductor integrated-circuit (IC) chip, and an underfill between the interposer and the first semiconductor integrated-circuit (IC) chip, wherein the underfill encloses the plurality of metal bumps.
15. The chip package of claim 1 , wherein the insulating dielectric layer comprises a polymer layer having a thickness greater than or equal to 3 micrometers.
16. The chip package of claim 1 , wherein the second interconnection metal layer comprises a metal line having a thickness between 2 and 10 micrometers.
17. The chip package of claim 1 , wherein the second interconnection metal layer comprises a copper layer and an adhesion layer at a bottom of the copper layer but not at a sidewall of the copper layer.
18. The chip package of claim 1 , wherein the insulating dielectric layer comprises silicon and has a thickness between 10 and 2,000 nanometers.
19. The chip package of claim 1 , wherein the first interconnection metal layer comprises a metal line having a thickness between 10 and 2,000 nanometers.
20. The chip package of claim 1 , wherein the first interconnection metal layer comprises a copper layer and an adhesion layer at a bottom and sidewall of the copper layer.