Runtime identification of bad memory cells based on difference between data pattern and read data
Technologies are provided for runtime identification of bad memory cells. An uncorrectable error can be detected in data stored in a plurality of memory cells of a memory device. Patterned data can be written to the plurality of memory cells that stored the data in which the uncorrectable error was detected. The data stored in the plurality of memory cells can be read and compared to the patterned data. One or more of the memory cells can be identified as bad memory cells based on differences between the patterned data and the data read from the plurality of memory cells. In at least some embodiments, the one or more identified bad memory cells can be omitted from subsequent data storage operations. Additionally or alternatively, the one or more identified bad memory cells can be repaired, for example, by using a post-package repair operation.
1. A random access memory device comprising:
a plurality of memory cells, organized in one or more logical data units, configured to store bits of data; and
a memory controller configured to:
detect an uncorrectable error in data stored in a plurality of memory cells of a first logical data unit of the one or more logical data units,
responsive to detecting the uncorrectable error, write bits of data conforming to a data pattern to the plurality of memory cells with the detected uncorrectable error,
read bits of data stored in the plurality of memory cells with the detected uncorrectable error,
identify a memory cell, of the plurality of memory cells with the detected uncorrectable error, that is a cause of the uncorrectable error based on a difference between the bits of data conforming to the data pattern and the bits of data read from the plurality of memory cells with the detected uncorrectable error,
transmit a message to a host computer connected to the random access memory device, reporting the identified memory cell,
receive a command from the host computer to perform a post-package repair operation targeting the identified memory cell, and
infer, based on the identifying the memory cell, that bad memory cells exist in a second logical data unit of the one or more logical data units, and
write bits of data conforming to the data pattern to memory cells in the second logical data unit and read data back from the written memory cells in the second logical data unit to confirm whether bad memory cells exist in the second logical data units.
2. The random access memory device of claim 1 , wherein the memory controller is further configured to avoid a use of the identified memory cell in a future data storage operation.
3. The random access memory device of claim 1 , further comprising a dynamic random access memory module that comprises the plurality of memory cells and the memory controller.
4. The random access memory device of claim 1 , wherein:
the random access memory device is an error-correcting code (ECC) memory device; and
the uncorrectable error is an error that cannot be corrected using an ECC.
5. A method, comprising:
detecting an uncorrectable error in data stored in a plurality of memory cells of a first logical data unit of a random access memory device;
responsive to the detecting the uncorrectable error, writing test data to the plurality of memory cells with the detected uncorrectable error;
reading data from the plurality of memory cells with the detected uncorrectable error;
identifying a bad memory cell, of the plurality of memory cells with the detected uncorrectable error, that is a cause of the uncorrectable error based on a difference between the data read from the plurality of memory cells with the detected uncorrectable error and the test data;
performing a post-package repair operation targeting the bad memory cell, and
inferring, based on the identifying the bad memory cell, that bad memory cells exist in a second logical data unit of the random access memory device, and
writing the test data to memory cells in the second logical data unit and reading data back from the written memory cells in the second logical data unit to confirm whether bad memory cells exist in the second logical data units.
6. The method of claim 5 , further comprising:
preventing use of the bad memory cell in a subsequent operation to store data in the random access memory device.
7. The method of claim 5 , wherein the post-package repair operation is performed subsequent to a reboot of the random access memory device.
8. The method of claim 5 , wherein:
the writing the test data comprises writing a series of ones to the plurality of memory cells; and
the identifying the bad memory cell comprises identifying a memory cell, of the plurality of memory cells, associated with a zero value in the data read from the plurality of memory cells.
9. The method of claim 5 , wherein the detecting the uncorrectable error comprises detecting an error that cannot be corrected using an error-correcting code.
10. The method of claim 5 , further comprising:
transmitting a message to an operating system of a host computer connected to the random access memory device, the message identifying the bad memory cell.
11. A system, comprising:
a random access memory device comprising a plurality of memory cells, organized in one or more logical data units, configured to store bits of data; and
a memory controller configured to:
detect an uncorrectable error in data stored in the plurality of memory cells of a first logical data unit of the one or more logical data units,
responsive to the detecting the uncorrectable error, write a bit pattern to the plurality of memory cells with the detected uncorrectable error,
read data from the plurality of memory cells with the detected uncorrectable error,
identify a bad memory cell, of the plurality of memory cells with the detected uncorrectable error, that is a cause of the uncorrectable error based on a difference between the data read from the plurality of memory cells with the detected uncorrectable error and the bit pattern, and
perform a repair operation targeting the bad memory cell.
12. The system of claim 11 , further comprising:
a host computer connected to the memory controller; and
wherein the memory controller is further configured to transmit a message to the host computer comprising an identity of the bad memory cell.
13. The system of claim 12 , wherein the host computer is configured to omit the bad memory cell from a future data write operation targeting the plurality of memory cells.
14. The system of claim 13 , wherein:
the plurality of memory cells are organized into multiple cache lines; and
the omitting the bad memory cell comprises omitting a cache line comprising the bad memory cell from the future data write operation.
15. The system of claim 11 , further comprising:
a boot firmware connected to the memory controller; and
wherein the memory controller is configured to transmit a message comprising an identity of the bad memory cell to the boot firmware.
16. The system of claim 15 , wherein the boot firmware is configured to transmit a command to the memory controller to perform the repair operation targeting the bad memory cell.
17. The system of claim 16 , wherein the boot firmware is configured to transmit the command to the memory controller as part of a reboot operation.
18. The system of claim 11 , wherein the detecting the uncorrectable error comprises detecting that an error that cannot be corrected using an error-correcting code.