Semiconductor memory device
A semiconductor memory device includes a substrate, first conductor layers, second conductor layers, a third conductor layer, and an insulator layer. The substrate includes a first region, a second region, and a third region separating the first and second regions. The first conductor layers are above the first region. The second conductor layers are above an uppermost one of the first conductor layers. The third conductor layer is above the second region. The insulator layer is above the second and third regions. The insulator layer includes first and second portions. The first portion is above the third conductor layer at a height from the substrate greater than a height of the uppermost one of the first conductor layers and extends along a substrate surface direction. The second portion extends along a substrate thickness direction and contacts a surface of the substrate in the third region.
1. A semiconductor memory device, comprising:
a substrate including a first region on which memory cells are provided, a second region on which a control circuit of the memory cells is provided, and a third region separating the first region and the second region;
a stack of first conductor layers spaced from each other above the first region of the substrate;
a stack of second conductor layers spaced from each other above an uppermost one of the first conductor layers;
a semiconductor pillar extending through the stack of first conductor layers and the stack of the second conductor layers;
a third conductor layer above the second region of the substrate;
a first insulator layer above the second and third regions of the substrate, the first insulator layer being not provided above the first region of the substrate, the first insulator layer including:
a first portion that is above the third conductor layer at a height from the substrate greater than a height of the uppermost one of the first conductor layers and extends along a surface direction of the substrate, and
a second portion that is continuous with the first portion, extends along a thickness direction of the substrate, and is in contact with a surface of the substrate in the third region;
a second insulator layer provided above the third region between the uppermost one of the first conductor layers and the lowermost one of the second conductor layers;
a third insulator layer between adjacent two of the first conductor layers; and
a fourth insulator layer between adjacent two of the second conductor layers, wherein
a thickness of the second insulator layer in the thickness direction is greater than a thickness of the third insulator layer and greater than a thickness of the fourth insulator layer.
2. The semiconductor memory device according to claim 1 , wherein each of the first conductor layers is a select gate line, and each of the second conductor layers is a word line of one or more of the memory cells.
3. The semiconductor memory device according to claim 2 , wherein the third conductor layer is a gate electrode of a transistor included in the control circuit.
4. The semiconductor memory device according to claim 1 , further comprising:
a stack of fourth conductor layers spaced from each other above an uppermost one of the second conductor layers, wherein
an uppermost one of the fourth conductor layers is at a height from the substrate greater than a height of the first insulator layer.
5. The semiconductor memory device according to claim 4 , further comprising:
a sixth insulator layer provided between the uppermost one of the second conductor layers and the lowermost one of the fourth conductor layers.
6. The semiconductor memory device according to claim 1 , wherein the height of the first portion of the first insulator layer is greater than a height of an uppermost one of the second conductor layers.
7. The semiconductor memory device according to claim 1 , wherein the first insulator layer is a silicon nitride film.
8. The semiconductor memory device according to claim 1 , further comprising:
a contact that extends through the first insulator layer along the thickness direction of the substrate and is in contact with the third conductor layer.
9. The semiconductor memory device according to claim 1 , wherein the second portion of the first insulator layer surrounds the second region of the substrate.
10. The semiconductor memory device according to claim 1 , wherein
the first conductor layers are spaced from each other at a first distance,
the second conductor layers are spaced from each other at a second distance, and
a distance between the uppermost one of the first conductor layers and a lowermost one of the second conductor layers is greater than the first distance and greater than the second distance.
11. The semiconductor memory device according to claim 1 , further comprising:
a fifth insulator layer above the second and third regions of the substrate and below the first portion of the first insulator layer, wherein
the fifth insulator layer includes:
a third portion that extends along the surface direction of the substrate, and
a fourth portion that is continuous with the third portion, extends along the thickness direction of the substrate, and is in contact with the surface of the substrate in the third region.
12. The semiconductor memory device according to claim 11 , wherein
the fourth portion of the fifth insulator layer surrounds the second region of the substrate, and
the second portion of the first insulator layer surrounds the fourth portion of the fifth insulator layer.
13. The semiconductor memory device according to claim 11 , wherein a thickness of the fifth insulator layer is uniform between the third portion and the fourth portion.
14. The semiconductor memory device according to claim 11 , wherein each of the first insulator layer and the fifth insulator layer is a silicon nitride film.
15. The semiconductor memory device according to claim 11 , wherein the third portion of the fifth insulator layer is at a height from the substrate greater than the height of the uppermost one of the first conductor layers.