Integrated circuit with asymmetric arrangements of memory arrays
An integrated circuit includes a first array of memory cells, a second array of memory cells, a first pair of complementary data lines, a second pair of complementary data lines, and a third pair of complementary data lines. The first pair of complementary data lines extend along the first array of memory cells, and are coupled to the first array of memory cells. The second pair of complementary data lines extend along the second array of memory cells, and are coupled to the first pair of complementary data lines. The third pair of complementary data lines extend along the second array of memory cells, and are coupled to the second array of memory cells. A number of rows of memory cells in the first array of memory cells is different from a number of rows of memory cells in the second array of memory cells.
1. An integrated circuit, comprising:
a first array of memory cells;
a second array of memory cells;
a first pair of complementary data lines extending along the first array of memory cells and terminating between the first array of memory cells and the second array of memory cells, wherein the first pair of complementary data lines are coupled to the first array of memory cells;
a second pair of complementary data lines extending along the second array of memory cells, wherein the second pair of complementary data lines are coupled to the first pair of complementary data lines; and
a third pair of complementary data lines extending along the second array of memory cells, wherein the third pair of complementary data lines are coupled to the second array of memory cells;
wherein a number of rows of memory cells in the first array of memory cells is different from a number of rows of memory cells in the second array of memory cells.
2. The integrated circuit of claim 1 , wherein the number of rows of memory cells in the first array of memory cells is smaller than the number of rows of memory cells in the second array of memory cells.
3. The integrated circuit of claim 1 , wherein lengths of the first pair of complementary data lines are different from lengths of the second pair of complementary data lines.
4. The integrated circuit of claim 1 , wherein lengths of the first pair of complementary data lines are shorter than lengths of the third pair of complementary data lines.
5. The integrated circuit of claim 1 , further comprising:
a plurality of word lines comprising:
a first group of word lines coupled to the first array of memory cells; and
a second group of word lines coupled to the second array of memory cells;
wherein a number of the first group of word lines is smaller than a number of the second group of word lines.
6. The integrated circuit of claim 1 , further comprising:
a selector circuit coupled to the second pair of complementary data lines and the third pair of complementary data lines,
wherein the selector circuit is configured to select, in response to a first control signal and a second control signal, the first array of memory cells or the second array of memory cells to be coupled to a sense amplifier.
7. The integrated circuit of claim 1 , further comprising:
a decoder circuit configured to generate, based on a word line address, a first control signal and a second control signal;
wherein data stored in a portion of the first array of memory cells or data stored in a portion of the second array of memory cells are configured to be accessed according to the first control signal and the second control signal.
8. The integrated circuit of claim 1 , further comprising:
an access circuit, comprising:
a precharge circuit coupled to the second pair of complementary data lines and the third pair of complementary data lines, and configured to precharge, according to a word line address, the first pair of complementary data lines coupled with the second pair of complementary data lines, and the second pair of complementary data lines or the third pair of complementary data lines; and
a selector circuit configured to selectively pass, in response to the word line address, signals from the first pair of complementary data lines through the second pair of complementary data lines to a sense amplifier, or signals from the third pair of complementary data lines to the sense amplifier.
9. An integrated circuit, comprising:
a plurality of memory cells comprising a first array of memory cells in a first number of rows and a second array of memory cells in a second number of rows, wherein the first number of rows and the second number of rows are different from each other;
a first pair of complementary data lines coupled to the first array of memory cells;
a second pair of complementary data lines coupled to the second array of memory cells;
a plurality of first word lines arranged in a first segment of a memory bank, and coupled to the first array of memory cells; and
a plurality of second word lines arranged in a second segment of the memory bank, that is disposed between the first segment and a sense amplifier, and the plurality of second word lines being coupled to the second array of memory cells;
wherein lengths of the first pair of complementary data lines are shorter than lengths of the second pair of complementary data lines;
wherein the plurality of first word lines and the plurality of second word lines are arranged according to a predetermined ratio of a number of the plurality of first word lines to a number of the plurality of second word lines;
wherein the predetermined ratio is less than 1.
10. The integrated circuit of claim 9 , wherein the predetermined ratio is substantially 1/3, 3/5, 7/9, 5/11 or 3/13.
11. The integrated circuit of claim 9 , wherein
the plurality of first word lines and the plurality of second word lines are configured to be activated according to a word line address;
wherein the word line address is associated with the predetermined ratio.
12. The integrated circuit of claim 9 , wherein the second array of memory cells occupy a greater area than that occupied by the first array of memory cells in a plan view.
13. The integrated circuit of claim 9 , further comprising:
a third pair of complementary data lines coupled to the first pair of complementary data lines;
wherein lengths of the third pair of complementary data lines are longer than lengths of the first pair of complementary data lines.
14. The integrated circuit of claim 13 , wherein
the first pair of complementary data lines and the second pair of complementary data lines are disposed in a first layer, and
the third pair of complementary data lines are disposed in a second layer different from the first layer.
15. The integrated circuit of claim 9 , further comprising:
a strap cell disposed between the first segment and the second segment;
wherein the first array of memory cells and the second array of memory cells are disposed at opposite sides of the strap cell;
wherein a number of rows of memory cells in the first array of memory cells is different from a number of rows of memory cells in the second array of memory cells.
16. The integrated circuit of claim 9 , further comprising:
a decoder circuit configured to generate, based on a word line address, a first control signal and a second control signal; and
an access circuit configured to be enabled, in response to the first control signal and the second control signal, to sense data stored in the first array of memory cells or data stored in the second array of memory cells.
17. A method, comprising:
generating, by a decoder circuit, based on a word line address, a first control signal and a second control signal;
activating, based on the word line address, one of a plurality of first word lines or one of a plurality of second word lines; and
accessing, in response to the first control signal and the second control signal, a memory cell coupled to an activated word line of the plurality of first word lines or the plurality of second word lines,
wherein the memory cell is in a first array of memory cells having a first number of rows or in a second array of memory cells having a second number of rows, wherein the first number of rows is smaller than the second number of rows;
wherein the first control signal and the second control signal are associated with a predetermined ratio of a number of the plurality of first word lines to a number of the plurality of second word lines.
18. The method of claim 17 , wherein the predetermined ratio is less than 1.
19. The method of claim 17 , wherein generating the first control signal and the second control signal comprises:
performing at least one logic operation with the word line address and outputting a logic signal as the first control signal; and
inverting, by an inverter, the logic signal to output an inverted logic signal as the second control signal.
20. The method of claim 17 , further comprising:
arranging alternatively the order of the plurality of first word lines and the plurality of second word lines; and
rearranging part of the plurality of first word lines to be a part of the plurality of second word lines.