Application architecture generation

1. An application architecture generation apparatus comprising:

at least one hardware processor;

an input receiver, executed by the at least one hardware processor, to

ascertain, for a project, an input that includes project information, component information, and target information;

a command line input analyzer, executed by the at least one hardware processor, to

parse the project information to determine whether the project is an existing project or a new project;

a configuration manager, executed by the at least one hardware processor, to generate a component list from the component information;

an architecture modeler, executed by the at least one hardware processor, to ascertain components from the component list based on installation paths;

a mapper, executed by the at least one hardware processor, to map each of the ascertained components to a corresponding target determined from the target information and to a template representing a structure for an application with respect to source code, by attaching, based on the installation paths identified in a configuration file associated with the project, a file associated with each of the ascertained components to the corresponding target;

a dependency manager, executed by the at least one hardware processor, to analyze a dependency for each of the ascertained components relative to at least one other component of the ascertained components; and

an integrated output generator, executed by the at least one hardware processor, to generate, based on the mapping and the analyzed dependency, an integrated output that includes an architecture for the application associated with the project.

2. The application architecture generation apparatus according to claim 1 , wherein the target includes at least one of a unit test target or a user interface test target.

3. The application architecture generation apparatus according to claim 1 , wherein the mapper is executed by the at least one hardware processor to map each of the ascertained components to the corresponding target determined from the target information and to the template representing the structure for an application with respect to source code by:

enabling a debugger flag with respect to the corresponding target.

4. The application architecture generation apparatus according to claim 1 , wherein the mapper is executed by the at least one hardware processor to map each of the ascertained components to the corresponding target determined from the target information and to the template representing the structure for an application with respect to source code by:

adding inline code with respect to the corresponding target.

5. The application architecture generation apparatus according to claim 1 , wherein the mapper is executed by the at least one hardware processor to map each of the ascertained components to the corresponding target determined from the target information and to the template representing the structure for an application with respect to source code by:

adding a bridging header with respect to the corresponding target.

6. The application architecture generation apparatus according to claim 1 , wherein the dependency manager is executed by the at least one hardware processor to

analyze the dependency for each of the ascertained components relative to at least one other component of the ascertained components, and

create or update a dependency based on the dependency analysis.

7. A method for application architecture generation comprising:

ascertaining, by an input receiver that is executed by at least one hardware processor, for a project, an input that includes project information, component information, and target information;

parsing, by a command line input analyzer that is executed by the at least one hardware processor, the project information to determine whether the project is an existing project or a new project;

generating, by a configuration manager that is executed by the at least one hardware processor, a component list from the component information;

ascertaining, by an architecture modeler that is executed by the at least one hardware processor, components from the component list based on installation paths identified in a configuration file associated with the project;

mapping, by a mapper that is executed by the at least one hardware processor, each of the ascertained components to a corresponding target determined from the target information and based on target type and to a template representing a structure for an application with respect to source code, by attaching, based on the installation paths, a file associated with each ascertained component of the ascertained components to the corresponding target;

analyzing, by a dependency manager that is executed by the at least one hardware processor, a dependency for each of the ascertained components relative to at least one other component of the ascertained components; and

generating, by an integrated output generator that is executed by the at least one hardware processor, based on the mapping and the analyzed dependency, an integrated output that includes an architecture for the application associated with the project.

8. The method according to claim 7 , wherein, in response to a determination that the project is the new project, further comprising:

ascertaining, by the architecture modeler that is executed by the at least one hardware processor, the components from the component list and architecture templates associated with the project; and

for each of the ascertained components, generating, by the architecture modeler that is executed by the at least one hardware processor, the corresponding target determined from the target information.

9. The method according to claim 7 , wherein the target includes at least one of a unit test target or a user interface test target.

10. A non-transitory computer readable medium having stored thereon machine readable instructions, the machine readable instructions, when executed by at least one hardware processor, cause the at least one hardware processor to:

ascertain, for a project, an input that includes project information, component information, and target information;

parse the project information to determine whether the project is an existing project or a new project;

generate a component list from the component information;

receive, at a workbench integrator that operates with a cartridge service, an indication of components that are to be ascertained from the component list;

ascertain, based on the received indication of the components from the component list and from a workbench repository, the components from the component list based on installation paths identified in a configuration file associated with the project;

map each of the ascertained components to a corresponding target determined from the target information and to a template representing a structure for an application with respect to source code, by attaching, based on the installation paths, a file associated with each ascertained component of the ascertained components to the corresponding target;

analyze a dependency for each of the ascertained components relative to at least one other component of the ascertained components; and

generate, based on the mapping and the analyzed dependency, an integrated output that includes an architecture for the application associated with the project.

11. The non-transitory computer readable medium according to claim 10 , wherein the instructions to ascertain, based on the received indication of the components from the component list and from the workbench repository, the components from the component list, are further to cause the at least one hardware processor to:

ascertain, via a representational state transfer (REST) application programming interface (API), the components from the component list.

12. The non-transitory computer readable medium according to claim 10 , wherein the target includes at least one of a unit test target or a user interface test target.