Varying-polarity read operations for polarity-written memory cells
Methods, systems, and devices for varying-polarity read operations for polarity-written memory cells are described. Memory cells may be programmed to store different logic values based on applying write voltages of different polarities to the memory cells. A memory device may read the logic values based on applying read voltages to the memory cells, and the polarity of the read voltages may vary such that at least some read voltages have one polarity and at least some read voltages have another polarity. The read voltage polarity may vary randomly or according to a pattern and may be controlled by the memory device or by a host device for the memory device.
1. A method, comprising:
receiving, at a memory device, a first read command to perform a first read operation for a memory cell, wherein the memory cell is operable to store one of a first logic value or a second logic value;
applying, in response to the first read command and as part of the first read operation, a first read voltage having a first polarity to the memory cell;
receiving, after the first read command, a second read command to perform a second read operation for the memory cell;
applying, in response to the second read command and as part of the second read operation, a second read voltage having a second polarity to the memory cell;
sensing the second logic value for the memory cell based at least in part on applying the second read voltage;
determining, after sensing the second logic value, an inverse of the second logic value based at least in part on the second read voltage having the second polarity, wherein the first logic value is the inverse of the second logic value; and
outputting, by the memory device, an indication of the first logic value based at least in part on the determining.
2. The method of claim 1 , further comprising:
receiving, before receiving the first read command, a write command associated with the first logic value for the memory cell;
applying, based at least in part on the write command, a write voltage having the first polarity to the memory cell, wherein the memory cell is operable to store the first logic value based at least in part on the write voltage having the first polarity;
determining, in response to the first read command, that the memory cell stores the first logic value based at least in part on applying the first read voltage; and
determining, in response to the second read command, that the memory cell stores the first logic value based at least in part on applying the second read voltage.
3. The method of claim 1 , further comprising:
sensing the first logic value for the memory cell based at least in part on applying the first read voltage; and
outputting, by the memory device, an additional indication of the first logic value based at least in part on the first logic value being sensed and the first read voltage having the first polarity.
4. The method of claim 1 , wherein:
the first read command indicates to use the first polarity for the first read voltage; and
the second read command indicates to use the second polarity for the second read voltage.
5. The method of claim 1 , further comprising:
determining to use the first polarity for the first read voltage based at least in part on a first random determination; and
determining to use the second polarity for the second read voltage based at least in part on a second random determination.
6. The method of claim 1 , further comprising:
determining to use the second polarity for the second read voltage based at least in part on the first read voltage having the first polarity.
7. The method of claim 1 , wherein the first read voltage and the second read voltage have a same magnitude.
8. The method of claim 1 , wherein the first read voltage and the second read voltage have a different magnitude.
9. A method, comprising:
receiving, at a memory device, a first read command for a memory cell, wherein the memory cell is operable to store one of a first logic value or a second logic value;
applying, based at least in part on the first read command, a first read voltage to the memory cell, the first read voltage having a first polarity;
receiving, after the first read command, a second read command for the memory cell;
applying, based at least in part on the second read command, a second read voltage to the memory cell, the second read voltage having a second polarity;
sensing the second logic value for the memory cell based at least in part on applying the second read voltage;
determining, after sensing the second logic value, an inverse of the second logic value based at least in part on the second read voltage having the second polarity, wherein the first logic value is the inverse of the second logic value; and
outputting, by the memory device, an indication of the first logic value based at least in part on the determining.
10. The method of claim 9 , further comprising:
receiving, before receiving the first read command, a write command associated with the first logic value for the memory cell;
applying, based at least in part on the write command, a write voltage having the first polarity to the memory cell, wherein the memory cell is operable to store the first logic value based at least in part on the write voltage having the first polarity;
determining, in response to the first read command, that the memory cell stores the first logic value based at least in part on applying the first read voltage; and
determining, in response to the second read command, that the memory cell stores the first logic value based at least in part on applying the second read voltage.
11. The method of claim 9 , further comprising:
sensing the first logic value for the memory cell based at least in part on applying the first read voltage; and
outputting, by the memory device, an additional indication of the first logic value based at least in part on the first logic value being sensed and the first read voltage having the first polarity.
12. The method of claim 9 , wherein:
the first read command indicates to use the first polarity for the first read voltage; and
the second read command indicates to use the second polarity for the second read voltage.
13. The method of claim 9 , further comprising:
determining to use the first polarity for the first read voltage based at least in part on a first random determination; and
determining to use the second polarity for the second read voltage based at least in part on a second random determination.
14. The method of claim 9 , further comprising:
determining to use the second polarity for the second read voltage based at least in part on the first read voltage having the first polarity.
15. The method of claim 9 , wherein the first read voltage and the second read voltage have a same magnitude.
16. The method of claim 9 , wherein the first read voltage and the second read voltage have a different magnitude.
17. A method, comprising:
applying, during a first read operation of a memory cell, a first read voltage to the memory cell, the first read voltage having a first polarity;
sensing, based at least in part on applying the first read voltage, a first logic value for the memory cell;
applying, during a second read operation of the memory cell, a second read voltage to the memory cell, the second read voltage having a second polarity;
sensing, based at least in part on applying the second read voltage, a second logic value for the memory cell, wherein the second logic value is an inverse of the first logic value; and
outputting, based at least in part on applying the second read voltage and sensing the second logic value, an indication of the first logic value.
18. The method of claim 17 , further comprising:
outputting, during the first read operation and based at least in part on applying the first read voltage and sensing the first logic value, an additional indication of the first logic value.