Analog to analog quantizer in crossbar array circuits for in-memory computing
Technologies relating to analog-to-analog quantizers with an intrinsic Rectified Linear Unit (ReLU) function designed for in-memory computing are disclosed. An apparatus, in some implementations, includes: a DAC; a first crossbar connected to the DAC; a first analog quantizer connected to the first crossbar; a buffer connected to the first analog quantizer; a second crossbar connected to the buffer; and an ADC connected to the second crossbar.
1. An apparatus comprising:
a digital-to-analog converter (DAC);
a first crossbar connected to the DAC;
a first analog quantizer connected to the first crossbar, wherein the first analog quantizer comprises:
a voltage divider set;
a comparator set having multiple comparators configured to generate voltage comparisons; and
a logic set, wherein the voltage divider is configured to divide a reference voltage into multiple divided reference voltages, wherein each divided reference voltage is configured to establish a respective reference voltage for each comparator of the comparator set, and wherein a voltage potential difference between adjacent divided reference voltages is substantially equal throughout the voltage divider set;
a buffer connected to the first analog quantizer;
a second crossbar connected to the buffer; and
an analog-to-digital converter (ADC) connected to the second crossbar.
2. The apparatus as claimed in claim 1 , wherein the first crossbar comprises a word line, a bit line, and a cross-point device formed between the word line and the bit line.
3. The apparatus as claimed in claim 2 , wherein the cross-point device comprises an RRAM (resistive random-access memory) device.
4. The apparatus as claimed in claim 1 , wherein the first crossbar is configured to perform in-memory computation.
5. The apparatus as claimed in claim 1 , wherein the buffer comprises a unity gain amplifier.
6. The apparatus as claimed in claim 1 , wherein the logic set is configured to output one of the respective reference voltages to the buffer based on the voltage comparisons.
7. The apparatus as claimed in claim 6 , wherein the logic set comprises one or more CMOS gates, one or more NOT gates, and one or more AND gates, each of the respective reference voltages connected to each of the CMOS gates.
8. The apparatus as claimed in claim 1 , wherein the voltage divider comprises multiple resistances serially connected between the reference voltage and a ground potential.
9. The apparatus as claimed in claim 1 , wherein the first analog quantizer has an intrinsic Rectified Linear Unit (ReLU) function.
10. The apparatus as claimed in claim 1 , wherein the comparator set is configured to generate digital values from outputs of each comparator to the logic set, the digital values are based on the voltage comparisons between an input voltage, and the respective reference voltages for each comparator.
11. An apparatus comprising:
a first digital-to-analog converter (DAC);
a first crossbar connected to the first DAC;
a first analog quantizer connected to the first crossbar;
a second digital-to-analog converter (DAC);
a second crossbar connected to the second DAC;
a second analog quantizer connected to the second crossbar;
a buffer connected to the first analog quantizer and the second analog quantizer; and
a third crossbar connected to the buffer; and an analog-to-digital converter (ADC) connected to the third crossbar.
12. The apparatus as claimed in claim 11 , wherein the buffer comprises a non-inverting summing amplifier.
13. The apparatus as claimed in claim 11 , wherein the buffer comprises a differential amplifier.
14. The apparatus as claimed in claim 11 , wherein the first crossbar, the second crossbar, and the third crossbar are configured to perform in-memory computation.