Two-terminal electronic charge resistance switching device

1. A two-terminal memory device comprising a bottom electrode electrically continuous with a first operating terminal of the device and a control gate electrode electrically continuous with a second operating terminal of the device, and further comprising a stack of insulator layers contactingly interposed between the bottom electrode and the control gate electrode, wherein:

the stack of insulator layers comprises a hopping conduction layer and a tunnel layer;

the tunnel layer is thinner than the hopping conduction layer and has a wider bandgap than the hopping conduction layer; and

the hopping conduction layer consists of a material that supports electron hopping transport.

2. The two-terminal memory device of claim 1 , wherein:

the bottom electrode is a metal layer disposed on a substrate;

the tunnel layer is an insulative layer that contacts and overlies the bottom electrode;

the hopping conduction layer is an insulative layer that contacts and overlies the tunnel layer; and

the control gate electrode is a metal layer disposed over the hopping conduction layer.

3. The two-terminal memory device of claim 2 , wherein the control gate electrode is disposed directly on the hopping conduction layer.

4. The two-terminal memory device of claim 2 , wherein the control gate electrode is disposed directly on a further insulator layer disposed on the hopping conduction layer.

5. The resistive memory device of claim 1 , wherein the tunnel layer comprises silicon dioxide and the hopping conduction layer comprises silicon nitride.

6. A method of information storage, comprising applying a charging bias voltage across a bilayer of different insulating material layers having an interface between them, wherein:

the bilayer consists of a tunnel layer and a hopping conduction layer;

the charging bias voltage is effective to tunnel electrons across the tunnel layer and across the interface, but is not effective to drive the tunneled electrons across the hopping conduction layer;

the method further comprises removing the charging bias voltage while the tunneled electrons are trapped at the interface;

the bilayer is included in a two-terminal memory device having only a first operating terminal and a second operating terminal;

the first operating terminal is electrically continuous with a bottom electrode, and the second operating terminal is electrically continuous with a control gate electrode;

the bilayer is contactingly interposed between the bottom electrode and the control gate electrode; and

the charging bias voltage is applied between the first operating terminal and the second operating terminal.

7. The method of claim 6 , further comprising erasing the bilayer before applying the charging bias voltage, wherein:

the erasing of the bilayer comprising applying a discharging bias voltage;

the discharging bias voltage is opposite in sign to the charging bias voltage;

the discharging bias voltage is effective to drive trapped electrons out of the hopping conduction layer, across the interface, and across the tunnel layer; and

the discharging bias voltage is applied between the first operating terminal and the second operating terminal.

8. A method of information retrieval, comprising applying a reading bias voltage across a bilayer of different insulating material layers having an interface between them, wherein:

the bilayer consists of a tunnel layer and a hopping conduction layer;

the reading bias voltage is effective to drive trapped electrons away from the interface and across the hopping conduction layer by electron hopping transport, but is ineffective to drive electrons across the tunnel layer;

the reading bias voltage is less than a threshold voltage for electron tunneling in the tunnel layer;

the bilayer is included in a two-terminal memory device having only a first operating terminal and a second operating terminal;

the first operating terminal is electrically continuous with a bottom electrode, and the second operating terminal is electrically continuous with a control gate electrode;

the bilayer is contactingly interposed between the bottom electrode and the control gate electrode; and

the reading bias voltage is applied between the first operating terminal and the second operating terminal.