Workload scheduler for memory allocation
Examples described herein relate to a work scheduler that includes at least one processor and at least one queue. In some examples, the work scheduler receives a request to allocate a region of memory and based on availability of a memory segment associated with a central cache to satisfy the request to allocate a region of memory, provide a memory allocation using an available memory segment entry associated with the central cache from the at least one queue. In some examples, the work scheduler assigns a workload to a processor and controls when to pre-fetch content relevant to the workload to store in a cache or memory accessible to the processor based on a position of the workload in a work queue associated with the processor.
1. An apparatus comprising:
an interface;
circuitry, coupled to the interface, the circuitry comprising a processor, the circuitry to:
cause pre-fetch of packet data and content associated with a workload to be stored in a cache accessible to the processor core based on a position of an identifier of the workload in a work queue associated with the processor, wherein the pre-fetch of the packet data causes copying of the packet data into the cache before processing of the packet data by the workload, wherein the pre-fetch of the content causes copying of: a software environment to process the packet data, cryptographic keys used to process the packet data, and instructions executed to process the packet data, and wherein the packet data associated with the workload includes packet payload and packet connection context; and
a second circuitry to determine whether to permit eviction or not permit eviction of the pre-fetched packet data in the cache based at least in part on a position of the identifier of the workload in the work queue.
2. The apparatus of claim 1 , wherein the circuitry is to pre-fetch the packet data associated with the workload by accessing a look-up table to determine one or more memory locations of packet data associated with the workload.
3. The apparatus of claim 1 , wherein the circuitry is to update the position of the identifier of the workload in the work queue based on completion of another workload identified in the work queue.
4. The apparatus of claim 1 , wherein based on the position of the identifier of the workload, the circuitry is to cause a pre-fetch of the packet data associated with the workload to store in the cache accessible to the processor core.
5. The apparatus of claim 1 , wherein the second circuitry is to prevent the packet data associated with the workload from being evicted from the cache based on the position of the identifier of the workload within an offset from a head of the work queue.
6. The apparatus of claim 1 , comprising a central processing unit (CPU) to offload data processing scheduling to the circuitry.
7. The apparatus of claim 1 , further comprising a server, data center, or rack, wherein the server, data center, or rack comprises a central processing unit (CPU) to offload work scheduling to the circuitry.
8. The apparatus of claim 1 , wherein the circuitry is to not cause pre-fetch of packet data that is stored in the cache.
9. The apparatus of claim 1 , wherein the workload comprises a packet processing workload based on Network Function Virtualization (NFV), software-defined networking (SDN), or virtualized network function (VNF).
10. The apparatus of claim 1 , wherein the packet data associated with the workload includes packet context comprising one or more of: Media Access Control (MAC) context information, Internet Protocol (IP) context information, or application context information.
11. The apparatus of claim 1 , wherein the second circuitry is to assign a priority level to the packet data in the cache based on the position indicator, wherein a high priority level is associated with the position indicator associated with a head of the work queue and a low priority level is associated with the position indicator associated with a bottom of the work queue, and wherein permission to evict the packet data is inverse to the priority level.
12. A method comprising:
assigning, using an offload circuitry, a workload to a processor;
the offload circuitry causing pre-fetch of packet data and content associated with the workload to a memory accessible to the processor based on a position of an identifier of the workload in a work queue associated with the processor, wherein the pre-fetched packet data associated with the workload includes packet payload and packet connection context, and the pre-fetched content includes a software environment to process the packet data, cryptographic keys, and instructions executed to process the packet data; and
adjusting an ability to evict at least a portion of the packet data associated with the workload from the memory, based on a change in the position of the identifier of the workload in the work queue, wherein the adjusting the ability to evict the at least a portion of the packet data associated with the workload comprises setting the ability to not evict based on the position of the identifier of the workload in the work queue being within an offset from a head of the work queue.
13. The method of claim 12 , comprising:
updating the position of the identifier of the workload in the work queue based on completion of another workload identified in the work queue.
14. The method of claim 12 , comprising:
reassigning the workload to another work queue based on load balancing of work among the processor and at least one other processor.