Method and memory used for reducing program disturbance by adjusting voltage of dummy word line

1. A method for reducing program disturbance of a memory, the memory comprising an upper deck and a lower deck, the upper deck being formed above the lower deck, the upper deck comprising a first upper dummy word line, the lower deck comprising a first lower dummy word line, the method comprising:

adjusting a first upper bias voltage applied to the first upper dummy word line and/or a first upper threshold voltage of the first upper dummy word line to adjust a first difference between the first upper bias voltage and the first upper threshold voltage; and

adjusting a first lower bias voltage applied to the first lower dummy word line and/or a first lower threshold voltage of the first lower dummy word line to adjust a second difference between the first lower bias voltage and the first lower threshold voltage.

2. The method of claim 1 , wherein:

the first difference is adjusted to be lower than a threshold; and

the second difference is adjusted to be lower than the threshold.

3. The method of claim 1 , wherein:

the first difference is adjusted to be higher than a threshold; and

the second difference is adjusted to be higher than the threshold.

4. The method of claim 1 , wherein the lower deck further comprises a second lower dummy word line, and the method further comprising:

adjusting a second lower bias voltage applied to the second lower dummy word line and/or a second lower threshold voltage of the second lower dummy word line to adjust a third difference between the second lower bias voltage and the second lower threshold voltage.

5. The method of claim 4 , wherein:

the first difference is adjusted to be higher than a threshold;

the second difference is adjusted to be lower than the threshold; and

the third difference is adjusted to be lower than the threshold.

6. The method of claim 4 , wherein a difference between the first difference and the second difference is within a predetermined range, and another difference between the first difference and the third difference is within the predetermined range.

7. The method of claim 1 , wherein the upper deck further comprises a second upper dummy word line, and the method further comprising:

adjusting a second upper bias voltage applied to the second upper dummy word line and/or a second upper threshold voltage of the second upper dummy word line to adjust a fourth difference between the second upper bias voltage and the second upper threshold voltage.

8. The method of claim 7 , wherein:

the first difference is adjusted to be lower than a threshold;

the second difference is adjusted to be lower than the threshold; and

the fourth difference is adjusted to be higher than the threshold.

9. The method of claim 8 , wherein a difference between the fourth difference and the first difference is within a predetermined range, and another difference between the fourth difference and the second difference is within the predetermined range.

10. The method of claim 1 , wherein the upper deck further comprises a second upper dummy word line, the lower deck further comprises a second lower dummy word line, and the method further comprising:

adjusting a second lower bias voltage applied to the second lower dummy word line and/or a second lower threshold voltage of the second lower dummy word line to adjust a third difference between the second lower bias voltage and the second lower threshold voltage; and

adjusting a second upper bias voltage applied to the second upper dummy word line and/or a second upper threshold voltage of the second upper dummy word line to adjust a fourth difference between the second upper bias voltage and the second upper threshold voltage.

11. The method of claim 10 , wherein:

the first difference is adjusted to be lower than a first threshold;

the second difference is adjusted to be lower than a second threshold;

the third difference is adjusted to be lower than the first threshold; and

the fourth difference is adjusted to be higher than the second threshold.

12. The method of claim 10 , wherein a difference between the fourth difference and the first difference is within a predetermined range, and another difference between the fourth difference and the second difference is within the predetermined range.

13. The method of claim 10 , wherein a difference between the fourth difference and the second difference is within a predetermined range, and another difference between the fourth difference and the third difference is within the predetermined range.

14. The method of claim 10 , further comprising:

setting the first upper bias voltage, the first lower bias voltage, the second lower bias voltage and the second upper bias voltage to a pre-pulse level during a pre-pulse operation; and

setting the first upper bias voltage, the first lower bias voltage, the second lower bias voltage and the second upper bias voltage to a program level during a program operation;

wherein and the pre-pulse level is higher than a maximum allowable level of the first upper threshold voltage, the first lower threshold voltage, the second lower threshold voltage and the second upper threshold voltage.

15. The method of claim 10 , further comprising:

setting the first upper bias voltage, the first lower bias voltage, the second lower bias voltage, and the second upper bias voltage to a first pre-pulse level, a second pre-pulse level, a third pre-pulse level and a fourth pre-pulse level respectively during a pre-pulse operation; and

setting the first upper bias voltage, the first lower bias voltage, the second lower bias voltage, and the second upper bias voltage to a first program level, a second program level, a third program level and a fourth program level respectively during a program operation;

wherein each of the first pre-pulse level, the second pre-pulse level, the third pre-pulse level and the fourth pre-pulse level is higher than a maximum allowable level of the first upper threshold voltage, the first lower threshold voltage, the second lower threshold voltage and the second upper threshold voltage.

16. A memory for reducing program disturbance, comprising:

an upper deck comprising a first upper dummy word line configured to receive a first upper bias voltage and have a first upper threshold voltage; and

an lower deck comprising a first lower dummy word line configured to receive a first lower bias voltage and have a first lower threshold voltage;

wherein the upper deck is formed above the lower deck, the first upper bias voltage and/or the first upper threshold voltage is adjusted to adjust a first difference between the first upper bias voltage and the first upper threshold voltage, and the first lower bias voltage and/or the first lower threshold voltage is adjusted to adjust a second difference between the first lower bias voltage and the first lower threshold voltage.

17. The memory of claim 16 , wherein the lower deck further comprises a second lower dummy word line configured to receive a second lower bias voltage and have a second lower threshold voltage, and the second lower bias voltage and/or the second lower threshold voltage is adjusted to adjust a third difference between the second lower bias voltage and the second lower threshold voltage.

18. The memory of claim 16 , wherein the upper deck further comprises a second upper dummy word line configured to receive a second upper bias voltage and have a second upper threshold voltage, and the second upper bias voltage and/or the second upper threshold voltage is adjusted to adjust a fourth difference between the second upper bias voltage and the second upper threshold voltage.

19. The memory of claim 16 , further comprising a joint oxide layer formed between the upper deck and the lower deck.

20. The memory of claim 16 , further comprising a select top gate electrode, a select word line, an unselect word line, a dummy word line, a select bit line and a bottom select gate electrode.