Semiconductor device and manufacturing method thereof
A device includes a first transistor, a second transistor, and a contact. The first transistor includes a first source/drain, a second source/drain, and a first gate between the first and second source/drains. The second transistor includes a third source/drain, a fourth source/drain, and a second gate between the third and fourth source/drains. The contact covers the first source/drain of the first transistor and the third source/drain of the second transistor. The contact is electrically connected to the first source/drain of the first transistor and electrically isolated from the third source/drain of the second transistor.
1. A device comprising:
a first transistor comprising a first source/drain, a second source/drain, and a first gate between the first and second source/drains;
a second transistor comprising a third source/drain, a fourth source/drain, and a second gate between the third and fourth source/drains; and
a contact covering the first source/drain of the first transistor and the third source/drain of the second transistor, wherein the contact is electrically connected to the first source/drain of the first transistor and electrically isolated from the third source/drain of the second transistor, and a bottom surface of a portion of the contact directly over the third source/drain of the second transistor is lower than a top surface of the first gate in a cross-sectional view.
2. The device of claim 1 , wherein the first gate of the first transistor is connected to the second gate of the second transistor.
3. The device of claim 1 , wherein the contact is further electrically connected to the first gate of the first transistor.
4. The device of claim 1 , wherein the contact is further electrically connected to the fourth source/drain of the second transistor.
5. The device of claim 1 , wherein the contact is electrically isolated from the second transistor.
6. A device comprising:
a first transistor comprising a first source/drain, a second source/drain, and a first gate between the first and second source/drains;
a second transistor comprising the second source/drain, a third source/drain, and a second gate between the second and third source/drains;
a third transistor comprising a fourth source/drain, a fifth source/drain, and a third gate between the fourth and fifth source/drains;
an isolation layer covering an entirety of the second source/drain of the first and second transistors, wherein a top surface of the isolation layer is lower than a top surface of the first gate in a cross-sectional view; and
a contact over and in contact with the fifth source/drain of the third transistor and the isolation layer.
7. The device of claim 6 , wherein the first transistor is one of a p-type transistor and an n-type transistor, and the third transistor is another of the p-type transistor and the n-type transistor.
8. The device of claim 6 , wherein the first transistor and the second transistor have the same conductivity type.
9. The device of claim 6 , further comprising:
a conductive trace over the first transistor and the second transistor; and
a first via electrically connected to the conductive trace and the contact.
10. The device of claim 9 , further comprising a second via electrically connected to the conductive trace and the third source/drain of the second transistor.
11. The device of claim 9 , further comprising a second via electrically connected to the conductive trace and the second gate of the second transistor.
12. The device of claim 9 , wherein the conductive trace overlaps with the first source/drain of the first transistor in a top view.
13. The device of claim 6 , wherein the first gate of the first transistor and the second gate of the second transistor are on opposite sides of the contact.
14. A device comprising:
a first transistor comprising a first source/drain, a second source/drain, and a first gate between the first and second source/drains;
a second transistor comprising a third source/drain, the second source/drain, and a second gate between the third and second source/drains;
an isolation layer covering the third source/drain of the second transistor;
a contact covering and in contact with the isolation layer, wherein a top surface of the contact is higher than a top surface of the isolation layer; and
a first conductive line electrically connected to the contact and the first gate of the first transistor.
15. The device of claim 14 , wherein the second gate of the second transistor is between the contact and the first gate of the first transistor.
16. The device of claim 14 , wherein an extension direction of the first conductive line is substantially perpendicular to an extension direction of the contact.
17. The device of claim 14 , wherein the isolation layer is in contact with opposite sidewalls of the third source/drain of the second transistor.
18. The device of claim 1 , further comprising an isolation structure extending from a bottom portion of the first source/drain to a bottom portion of the third source/drain, wherein the contact is in contact with the isolation structure.
19. The device of claim 1 , further comprising a spacer structure on a sidewall of the second gate, wherein a top surface of a portion of the contact directly over the third source/drain of the second transistor is equal to or lower than a top surface of the spacer structure.
20. The device of claim 6 , wherein the contact is in contact with a top surface of the isolation layer.