IP Library › Granted Patent US 11,417,611
Granted Patent B2
US 11,417,611 · App. 16/801,093 · Granted Aug 16, 2022

Devices and methods for reducing stress on circuit components

Inventors: Padraig Fitzgerald (Mallow, IE); George Redfield Spalding, Jr. (Edinburgh, GB); Jonathan Ephraim David Hurwitz (Edinburgh, GB); Michael J. Flynn (Woodhaven, IE)
Assignee: Analog Devices International Unlimited Company
H01L23/562H01L21/30604H01L21/8234H01L23/528H01L27/0629H01L21/0273
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Quick Facts
Patent No.
US 11,417,611
App. No.
16/801,093
Granted
Aug 16, 2022
Kind
B2
Abstract

The present disclosure relates to integrated circuits which include various structural elements designed to reduce the impact of strain on the electronic components of the circuit. In particular, a combination of trenches and cavities are used to mechanically isolate the integrated circuit from the surrounding substrate. The trenches may be formed such that they surround the integrated circuit, and the cavities may be formed under the integrated circuit. As such, the integrated circuit may be formed on a portion of the substrate that forms a platform. In order that the platform does not move, it may be tethered to the surrounding substrate. By including such mechanical elements, variation in the electrical characteristics of the integrated circuit are reduced.

Claims (24)

1. An integrated circuit, comprising:

an integrated circuit die having one or more stress-sensitive circuits including active circuit components formed on or adjacent to a first surface of the integrated circuit die;

one or more trenches formed around the one or more stress-sensitive circuits; and

one or more cavities, formed underneath the one or more stress-sensitive circuits and having rounded edges.

2. The integrated circuit of claim 1 , wherein the one or more cavities are physically coupled to the one or more trenches.

3. The integrated circuit of claim 1 , wherein the one or more cavities extend underneath the one or more trenches.

4. The integrated circuit of claim 1 , wherein the one or more trenches and the one or more cavities are configured to form a circuit platform, in the integrated circuit die, the one or more stress-sensitive circuits being formed on the circuit platform.

5. The integrated circuit of claim 4 , wherein the one or more trenches and the one or more cavities are configured to form one or more tethers, each tether physically coupling the circuit platform to the surrounding integrated circuit die.

6. The integrated circuit of claim 5 , wherein each tether couples a respective first point on the circuit platform to a respective second point on the surrounding integrated circuit die, the first and second points being at different circumferential locations.

7. The integrated circuit of claim 6 , wherein the circuit platform and the surrounding integrated circuit die have a plurality of corners, the corners of the circuit platform aligned with respective corners of the integrated circuit die, and wherein each of the one or more tethers is coupled between a corner of the circuit platform and a corner of the integrated circuit die which is not aligned with the respective corner of the circuit platform.

8. The integrated circuit of claim 7 , wherein each tether includes a portion which is arranged to be substantially parallel to a respective side of the circuit platform.

9. The integrated circuit of claim 5 , further comprising one or more conductive tracks, formed along one or more of the tethers, for coupling the one or more stress-sensitive circuits to external connections.

10. The integrated circuit of claim 4 , wherein the one or more trenches are L-shaped; and a corner of each L-shaped trench is aligned with a corner of the circuit platform.

11. The integrated circuit of claim 4 , wherein a pedestal is formed underneath the circuit platform, coupling the circuit platform to the integrated circuit die.

12. The integrated circuit of claim 1 , wherein the one or more stress-sensitive circuits include passive circuit components, and the active or the passive circuit components are stress-sensitive.

13. An integrated circuit, comprising:

an integrated circuit die having an active circuit component;

a trench formed through a portion of the integrated circuit die adjacent the active circuit component; and

a cavity formed in the integrated circuit die underneath at least a portion of the active circuit component, wherein the cavity includes rounded edges.

14. The integrated circuit of claim 13 , wherein the cavity is physically coupled to the trench.

15. The integrated circuit of claim 13 , wherein the trench separates the active circuit component from a neighboring area of the integrated circuit die, wherein the integrated circuit further comprises a tether physically coupling the neighboring area of the integrated circuit die to the active circuit component.

16. The integrated circuit of claim 13 , further comprising a pedestal formed on the integrated circuit die and supporting the active integrated circuit, wherein the pedestal extends through the cavity.

17. The integrated circuit of claim 1 , wherein the one or more trenches are lined with sidewall protection.

18. The integrated circuit of claim 13 , wherein the trench is lined with sidewall protection.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 25, 2020
From: FITZGERALD, PADRAIG; SPALDING, GEORGE REDFIELD, JR.; HURWITZ, JONATHAN EPHRAIM DAVID; FLYNN, MICHAEL J.
To: ANALOG DEVICES INTERNATIONAL UNLIMITED COMPANY
Reel/Frame 053882/0727 →
Continuity (1)
Related Publication 20210265281A1 · Aug 26, 2021
Cited By (1)
US 12,612,303