Transistors with different threshold voltages

1. A method comprising:

providing a workpiece comprising a substrate, first vertically stacked channel members in a first area of the substrate, second vertically stacked channel members in a second area of the substrate, and third vertically stacked channel members in a third area of the substrate;

depositing a gate dielectric layer over the first vertically stacked channel members, the second vertically stacked channel members, and the third vertically stacked channel members;

depositing a sacrificial layer over the gate dielectric layer;

etching the sacrificial layer such that a portion of the sacrificial layer remains disposed between adjacent ones of the first vertically stacked channel members, the second vertically stacked channel members, and the third vertically stacked channel members;

selectively removing all of the sacrificial layer in the second area;

depositing a first work function layer over the first vertically stacked channel members, the second vertically stacked channel members, and the third vertically stacked channel members;

selectively removing the first work function layer and the sacrificial layer in the first area;

depositing a second work function layer over the first vertically stacked channel members, the second vertically stacked channel members, and the third vertically stacked channel members, the second work function layer being different from the first work function layer; and

depositing a passivation layer over the second work function layer.

2. The method of claim 1 , wherein the providing of the workpiece comprises:

forming a plurality of alternating semiconductor layers over the first area, the second area, and the third area of the substrate, the plurality of alternating semiconductor layers comprising a first plurality of first semiconductor layers interleaved by a second plurality of second semiconductor layers;

patterning the plurality of alternating semiconductor layers to form a first active region in the first area, a second active region in the second area, and a third active region in the third area; and

selectively removing the second plurality of second semiconductor layers to form the first vertically stack channel members in the first active region, and the second vertically stacked channel members in the second active region, and the third vertically stacked channel members in the third active region.

3. The method of claim 1 , wherein the etching of the sacrificial layer exposes the gate dielectric layer deposited over side surfaces of the first vertically stacked channel members, the second vertically stacked channel members, and the third vertically stacked channel members.

4. The method of claim 1 , wherein the sacrificial layer comprises silicon oxide or silicon nitride.

5. The method of claim 1 ,

wherein the first work function layer comprises aluminum (Al), titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), tantalum aluminum carbide (TaAlC), tantalum aluminum silicide (TaSiAl), tantalum silicon carbide (TaSiC), tantalum silicide (TaSi), or hafnium carbide (HfC),

wherein the second work function layer comprises titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum nitride (TaN), tungsten carbonitride (WCN), or molybdenum (Mo).

6. The method of claim 1 , wherein the passivation layer comprises titanium nitride (TiN), titanium silicon nitride (TiSiN), silicon (Si), tantalum nitride (TaN), or tungsten carbonitride (WCN).

7. The method of claim 1 , further comprising:

selectively removing the passivation layer, the first work function layer, the second work function layer, and the sacrificial layer in the third area;

depositing a glue layer over the first vertically stacked channel members, the second vertically stacked channel members, and the third vertically stacked channel members; and

depositing a metal fill layer over the glue layer.

8. The method of claim 7 ,

wherein the glue layer comprises titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum nitride (TaN), tungsten carbonitride (WCN), or molybdenum (Mo),

wherein the metal fill layer comprises tungsten (W) or cobalt (Co).

9. A method comprising:

providing a workpiece comprising a substrate, first vertically stacked channel members in a first area of the substrate, second vertically stacked channel members in a second area of the substrate, and third vertically stacked channel members in a third area of the substrate;

depositing a gate dielectric layer over the first vertically stacked channel members, the second vertically stacked channel members, and the third vertically stacked channel members;

depositing a sacrificial layer over the gate dielectric layer;

partially and selectively etching the sacrificial layer such that a portion of the sacrificial layer is disposed between adjacent ones of the first vertically stacked channel members, the second vertically stacked channel members, and the third vertically stacked channel members;

selectively removing all of the sacrificial layer in the second area;

depositing a first work function layer over the first vertically stacked channel members, the second vertically stacked channel members, and the third vertically stacked channel members;

selectively removing the first work function layer and the sacrificial layer in the first area,

depositing a second work function layer over the first vertically stacked channel members, the second vertically stacked channel members, and the third vertically stacked channel members, the second work function layer being different from the first work function layer;

depositing a passivation layer over the second work function layer;

selectively removing the passivation layer, the first work function layer, the second work function layer, and the sacrificial layer in the third area;

selectively removing the passivation layer, the first work function layer, the second work function layer, and the sacrificial layer in the third area;

depositing a glue layer over the first vertically stacked channel members, the second vertically stacked channel members, and the third vertically stacked channel members; and

depositing a metal fill layer over the glue layer,

wherein the first work function layer is different from the second work function layer,

wherein a composition of the first work function layer is substantially identical to a composition of the glue layer.

10. The method of claim 9 , wherein the second work function layer comprises aluminum (Al).

11. The method of claim 10 , wherein the portion of the sacrificial layer disposed between adjacent ones of the third vertically stacked channel members prevents the first work function layer and second work function layer from being deposited between adjacent ones of the third vertically stacked channel members.

12. The method of claim 9 ,

wherein the selectively removing all of the sacrificial layer in the second area comprises use of an etchant having an etching selectivity to the sacrificial layer.

13. A method comprising:

forming a first plurality of channel members, a second plurality of channel members, and a third plurality of channel members over a substrate;

depositing a gate dielectric layer over and around each of the first plurality of channel members, each of the second plurality of channel members, and each of the third plurality of channel members;

after the depositing of the gate dielectric layer, forming a first work function layer around each of the second plurality of channel members;

after the selectively forming of the first work function layer, forming a second work function layer around each of the first plurality of channel members and each of the second plurality of channel members;

depositing a passivation layer over the first plurality of channel members, the second plurality of channel members, and the third plurality of channel members;

selectively removing the first work function layer, the second work function layer, and the passivation layer over the third plurality of channel members to expose the gate dielectric layer around each of the third plurality of channel members; and

depositing a glue layer over the first plurality of channel members, the second plurality of channel members, and the third plurality of channel members.

14. The method of claim 13 ,

wherein the first plurality of channel members are vertically stacked one over another,

wherein the second plurality of channel members are vertically stacked one over another,

wherein the third plurality of channel members are vertically stacked one over another.

15. The method of claim 13 , wherein forming the first work function layer comprises depositing the first work function layer over the first plurality of channel members and the third plurality of channel members,

wherein the first work function layer does not wrap around each of the first plurality of channel members,

wherein the first work function layer does not wrap around each of the third plurality of channel members.

16. The method of claim 15 , wherein forming the first work function layer further comprises forming sacrificial features between adjacent channel members of the first plurality of channel members and between adjacent channel members of the third plurality of channel members.

17. The method of claim 16 , wherein the sacrificial features comprise silicon oxide or silicon nitride.

18. The method of claim 13 ,

wherein the first work function layer comprises aluminum (Al), titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), tantalum aluminum carbide (TaAlC), tantalum aluminum silicide (TaSiAl), tantalum silicon carbide (TaSiC), tantalum silicide (TaSi), or hafnium carbide (HfC),

wherein the second work function layer comprises titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum nitride (TaN), tungsten carbonitride (WCN), or molybdenum (Mo).

19. The method of claim 13 , wherein the passivation layer comprises titanium nitride (TiN), titanium silicon nitride (TiSiN), silicon (Si), tantalum nitride (TaN), or tungsten carbonitride (WCN).

20. The method of claim 19 ,

wherein the glue layer comprises titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum nitride (TaN), tungsten carbonitride (WCN), or molybdenum (Mo).