MRAM stacks, MRAM devices and methods of forming the same
Memory stacks, memory devices and method of forming the same are provided. A memory stack includes a spin-orbit torque layer, a magnetic bias layer and a free layer. The magnetic bias layer is in physical contact with the spin-orbit torque layer and has a first magnetic anisotropy. The free layer is disposed adjacent to the spin-orbit torque layer and has a second magnetic anisotropy perpendicular to the first magnetic anisotropy.
1. A memory stack, comprising:
a spin-orbit torque layer;
a magnetic bias layer being in direct contact with the spin-orbit torque layer and having a first magnetic anisotropy; and
a free layer disposed adjacent to the spin-orbit torque layer and having a second magnetic anisotropy perpendicular to the first magnetic anisotropy.
2. The memory stack of claim 1 , wherein the magnetic bias layer and the free layer are at the same side of the spin-orbit torque layer.
3. The memory stack of claim 2 , further comprising a non-magnetic metal spacer between the magnetic bias layer and the free layer, wherein the non-magnetic metal spacer includes PtCo, WCoFeB, Ru, RuFe, RuCo, Ir, IrFe, IrCo or a combination thereof.
4. The memory stack of claim 1 , wherein the magnetic bias layer and the free layer are at opposite sides of the spin-orbit torque layer.
5. The memory stack of claim 1 , wherein a width of the magnetic bias layer is substantially equal to a width of the free layer.
6. The memory stack of claim 1 , wherein a width of the magnetic bias layer is greater than a width of the free layer.
7. The memory stack of claim 1 , wherein the free layer comprises FeCo, CoFeB, FeB or a combination thereof, and the magnetic bias layer comprises Co, CoNi or a combination thereof.
8. A memory stack, comprising:
a spin-orbit torque layer;
a synthetic free layer disposed over the spin-orbit torque layer and comprising:
a first free layer with a perpendicular magnetic anisotropy; and
a second free layer with a horizontal magnetic anisotropy;
a tunneling barrier layer disposed over the synthetic free layer; and
a reference layer disposed over the tunneling barrier layer.
9. The memory stack of claim 8 , wherein the first free layer is in physical contact with the spin-orbit torque layer.
10. The memory stack of claim 8 , wherein the synthetic free layer further comprises a non-magnetic metal spacer between the first free layer and the second free layer.
11. The memory stack of claim 8 , wherein the second layer of the synthetic free layer is oriented in the (100) direction.
12. The memory stack of claim 8 , further comprising a capping structure disposed over the reference layer, wherein the capping structure comprises Ta, Ru or a combination thereof.
13. The memory stack of claim 12 , further comprising a synthetic antiferromagnetic layer disposed between the capping structure and the reference layer.
14. The memory stack of claim 13 , wherein the synthetic antiferromagnetic layer is oriented in the (111) direction or the (100) direction.
15. The memory stack of claim 8 , wherein the tunneling barrier layer is oriented in the (100) direction.
16. The memory stack of claim 8 , wherein the reference layer is oriented in the (100) direction.
17. A memory device, comprising:
a substrate;
a first transistor disposed over the substrate and having a first source/drain region;
a second transistor disposed over the substrate and having a second source/drain region; and
a MRAM cell disposed over the substrate and comprising:
first and second bottom electrodes respectively coupled to the first source/drain region and the second source/drain region;
a spin-orbit torque layer disposed over the first and second bottom electrodes;
a synthetic free layer disposed over the spin-orbit torque layer and comprising two layers configured to have magnetic anisotropies perpendicular to each other;
a tunneling barrier layer disposed over the synthetic free layer;
a reference layer disposed over the tunneling barrier layer; and
a top electrode disposed over the reference layer and coupled to a bit line.
18. The memory device of claim 17 , wherein the layer of the synthetic free layer that is in physical contact with the spin-orbit torque layer forms a perpendicular magnetic anisotropy with the spin-orbit torque layer.
19. The memory device of claim 17 , further comprising a dummy transistor between first transistor and the second transistor, wherein the dummy transistor is grounded.
20. The memory device of claim 17 , wherein the tunneling barrier layer, the reference layer and part of the synthetic free layer are all oriented in the (100) direction.