Memory system

1. A memory system comprising:

a nonvolatile memory;

a buffer configured to temporarily store a plurality of data bits to be written to the nonvolatile memory; and

a controller configured to:

write the plurality of data bits, read from the buffer, to the nonvolatile memory;

write a plurality of intermediate parity bits to the buffer, but not to the nonvolatile memory, wherein each of the plurality of intermediate parity bits is associated with an error correction process on each of the plurality of data bits; and

write, to the nonvolatile memory, an accumulated parity bit that is an integration of the plurality of intermediate parity bits.

2. The memory system according to claim 1 , wherein the controller is configured to discard the plurality of intermediate parity bits when writing the plurality of data bits corresponding to the accumulated parity bit to the nonvolatile memory is determined to be successful.

3. The memory system according to claim 2 , wherein the controller is configured to generate the plurality of intermediate parity bits by performing an encoding operation for the error correction process on each of the plurality of data bits, and generate the accumulated parity bit by performing a predetermined operation on the plurality of generated intermediate parity bits.

4. The memory system according to claim 3 , wherein the plurality of data bits include a plurality of first data bits and a plurality of second data bits,

the plurality of intermediate parity bits include a plurality of first intermediate parity bits that correspond to the plurality of first data bits, and a second intermediate parity bit that corresponds to the second data bits, and wherein

the controller is configured to:

read the accumulated parity bit from the nonvolatile memory;

read the plurality of first data bits from the nonvolatile memory;

perform the encoding operation for the error correction process on the plurality of first data bits to generate the plurality of first intermediate parity bits;

read the second data from the nonvolatile memory;

generate the second intermediate parity bit on the basis of the plurality of first intermediate parity bits and the accumulated parity bit; and

correct the second data bit using the second intermediate parity bit.

5. The memory system according to claim 3 , wherein the predetermined operation is an exclusive OR or an encoding operation for an error correction process.

6. The memory system according to claim 1 , wherein a bit length of the accumulated parity bit is shorter than a sum of respective bit lengths of the plurality of intermediate parity bits.

7. The memory system according to claim 1 , wherein the plurality of data bits are stored in respective areas in the nonvolatile memory that are arranged to be physically dispersed from each other.

8. A method of operating a memory system, the method comprising:

writing a plurality of data bits temporarily stored in a buffer, to a nonvolatile memory;

writing a plurality of intermediate parity bits to the buffer but not to the nonvolatile memory, each of the plurality of intermediate parity bits associated with an error correction process on each of the plurality of data bits; and

writing, to the nonvolatile memory, an accumulated parity bit that is an integration of the plurality of intermediate parity bits.

9. The method according to claim 8 , further comprising:

discarding the plurality of intermediate parity bits when writing the plurality of data bits corresponding to the accumulated parity bit to the nonvolatile memory is successful.

10. The method according to claim 8 , further comprising:

generating the plurality of intermediate parity bits by performing an encoding operation for the error correction process on each of the plurality of data bits; and

generating the accumulated parity bit by performing a predetermined operation on the plurality of generated intermediate parity bits.

11. The method according to claim 10 , wherein the plurality of data bits include a plurality of first data bits and a second data bit,

the plurality of intermediate parity bits include a plurality of first intermediate parity bits that correspond to the plurality of first data bits, and a second intermediate parity bit that corresponds to the second data bit, the method further comprises:

reading the accumulated parity bit from the nonvolatile memory;

reading the plurality of first data bits from the nonvolatile memory;

performing the encoding operation for the error correction process on the plurality of first data bits to generate the plurality of first intermediate parity bits;

reading the second data bit from the nonvolatile memory;

generating the second intermediate parity bit on the basis of the plurality of first intermediate parity bits and the accumulated parity bit; and

correcting the second data bit using the second intermediate parity bit.

12. The method according to claim 10 , wherein the predetermined operation is exclusive OR or an encoding operation for an error correction process.

13. The method according to claim 8 , wherein a bit length of the accumulated parity bit is shorter than a sum of respective bit lengths of the plurality of intermediate parity bits.

14. The method according to claim 8 , wherein the plurality of data bits are stored in respective areas in the nonvolatile memory that are arranged to be physically dispersed from each other.

15. A memory system connectable to a host comprising:

a nonvolatile memory; and

a controller configured to:

write the plurality of data bits received from the host and not yet been written to the nonvolatile memory, to the nonvolatile memory;

generate a plurality of intermediate parity bits, wherein each of the plurality of intermediate parity bits is associated with an error correction process on each of the plurality of data bits; and

write, to the nonvolatile memory, not the plurality of intermediate parity bits but an accumulated parity bit that is an integration of the plurality of intermediate parity bits.

16. The memory system according to claim 15 , wherein the controller is configured to discard the plurality of intermediate parity bits when writing the plurality of data bits corresponding to the accumulated parity bit to the nonvolatile memory is determined to be successful.

17. The memory system according to claim 16 , wherein the controller is configured to generate the plurality of intermediate parity bits by performing an encoding operation for the error correction process on each of the plurality of data bits, and generate the accumulated parity bit by performing a predetermined operation on the plurality of generated intermediate parity bits.

18. The memory system according to claim 17 , wherein the plurality of data bits include a plurality of first data bits and a plurality of second data bits,

the plurality of intermediate parity bits include a plurality of first intermediate parity bits that correspond to the plurality of first data bits, and a second intermediate parity bit that corresponds to the second data bits, and wherein

the controller is configured to:

read the accumulated parity bit from the nonvolatile memory;

read the plurality of first data bits from the nonvolatile memory;

perform the encoding operation for the error correction process on the plurality of first data bits to generate the plurality of first intermediate parity bits;

read the second data from the nonvolatile memory;

generate the second intermediate parity bit on the basis of the plurality of first intermediate parity bits and the accumulated parity bit; and

correct the second data bit using the second intermediate parity bit.

19. The memory system according to claim 17 , wherein the predetermined operation is an exclusive OR or an encoding operation for an error correction process.

20. The memory system according to claim 15 , wherein a bit length of the accumulated parity bit is shorter than a sum of respective bit lengths of the plurality of intermediate parity bits.