Memory arrays comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells

1. A method used in forming a memory array comprising strings of memory cells, comprising:

forming a conductor tier comprising conductor material on a substrate;

forming a stack comprising vertically-alternating first tiers and second tiers above the conductor tier, the stack comprising laterally-spaced memory-block regions having horizontally-elongated trenches there-between, channel-material strings extending through the first tiers and the second tiers, material of the first tiers being of different composition from that of the second tiers, a lowest of the first tiers being thicker than the first tiers there-above;

isotropically etching the first-tier material selectively relative to the second-tier material to form void-space in the first tiers;

depositing conducting material into the trenches and into the void-space in the first tiers, the conducting material filling the void-space in the first tiers that are above the lowest first tier, the conducting material less-than-filling the void-space in the lowest first tier;

etching the conducting material from the lowest first tier; and

after the etching of the conducting material, depositing conductive material into the void-space of the lowest first tier and that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier.

2. The method of claim 1 comprising etching away all of the conducting material that is in the trenches before depositing the conductive material.

3. The method of claim 1 wherein at least an uppermost portion of the conductor material of the conductor tier is of the same composition as the conductive material.

4. The method of claim 1 wherein the lowest first tier is at least 1.5 times thicker than the first tiers there-above.

5. The method of claim 1 wherein the lowest first tier is not directly against the conductor material of the conductor tier during the isotropically etching.

6. The method of claim 5 wherein a lowest of the second tiers is vertically between the conductor material of the conductor tier and the lowest first tier during the isotropically etching.

7. The method of claim 6 wherein the lowest second tier is thinner than the second tiers there-above during the isotropically etching.

8. The method of claim 7 wherein a next-lowest of the second tiers above the lowest second tier is thicker than the second tiers there-above during the isotropically etching.

9. The method of claim 1 wherein the conductive material is of different composition from that of at least an uppermost portion of the conductor material of the conductor tier.

10. The method of claim 1 wherein a lowest surface of the channel material of the channel-material strings is never directly against any of the conductor material of the conductor tier.

11. The method of claim 1 wherein the conductive material in the void-space of the lowest first tier is directly against a sidewall of the channel material of the channel-material strings.

12. The method of claim 1 wherein the conductive material in the void-space of the lowest first tier is directly against an uppermost surface of the conductor material of the conductor tier.

13. The method of claim 1 wherein,

the conductive material in the void-space of the lowest first tier is directly against a sidewall of the channel material of the channel-material strings; and

the conductive material in the void-space of the lowest first tier is directly against an uppermost surface of the conductor material of the conductor tier.

14. The method of claim 1 comprising forming intervening material laterally-between and longitudinally-along immediately-laterally-adjacent of the memory-block regions, the intervening material comprising insulating material that is directly against the conductor material of the conductor tier; and

wherein the conducting material of the second tiers that are above the lowest second tier project laterally in a direction away from the channel-material strings into the insulating material of the intervening material in a finished circuitry construction.

15. The method of claim 1 comprising forming intervening material laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks, the intervening material comprising insulating material that is directly against the conductor material of the conductor tier, the insulating material of the intervening material projecting laterally in a direction towards the channel-material strings to be directly under a lowest of the second tiers in a finished circuitry construction.

16. A method used in forming a memory array comprising strings of memory cells, comprising:

forming a conductor tier comprising conductor material on a substrate;

forming a stack comprising vertically-alternating first tiers and second tiers above the conductor tier, the stack comprising laterally-spaced memory-block regions having horizontally-elongated trenches there-between, channel-material strings extending through the first tiers and the second tiers, material of the first tiers being of different composition from that of the second tiers, a lowest of the first tiers being thicker than the first tiers there-above, a lowest of the second tiers being thinner than the second tires there-above and being directly against a top of the conductor material of the conductor tier;

isotropically etching the first-tier material selectively relative to the second-tier material to form void-space in the first tiers;

depositing conducting material into the trenches and into the void-space in the first tiers, the conducting material filling the void-space in the first tiers that are above the lowest first tier, the conducting material less-than-filling the void-space in the lowest first tier;

etching the conducting material from the lowest first tier;

after the etching of the conducting material, etching the second-tier material of the lowest second tier to expose the conductor material of the conductor tier that was there-beneath;

exposing a sidewall of the channel material of the channel-material strings; and

depositing conductive material into the void-space of the lowest first tier directly against the exposed sidewall of the channel material of the channel-material strings and directly against an uppermost surface of the conductor material of the conductor tier.

17. The method of claim 16 wherein at least an uppermost portion of the conductor material of the conductor tier is of the same composition as the conductive material.

18. The method of claim 16 wherein the lowest first tier is at least 1.5 times thicker than the first tiers there-above.

19. The method of claim 16 wherein a lowest surface of the channel material of the channel-material strings is never directly against any of the conductor material of the conductor tier.

20. The method of claim 16 wherein conducting material is in the second tiers in a finished circuitry construction, and comprising:

forming intervening material laterally-between and longitudinally-along immediately-laterally-adjacent of the memory block regions, the intervening material comprising insulating material that is directly against the conductor material of the conductor tier; and

wherein the conducting material of the second tiers that are above the lowest second tier project laterally in a direction away from the channel-material strings into the insulating material of the intervening material in the finished circuitry construction.

21. The method of claim 16 comprising forming intervening material laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks, the intervening material comprising insulating material that is directly against the conductor material of the conductor tier, the insulating material of the intervening material projecting laterally in a direction towards the channel-material strings to be directly under a lowest of the first tiers.