Diffusion barrier layer in programmable metallization cell
Some embodiments relate to a memory device. The memory device includes a bottom electrode overlying a substrate. A data storage layer overlies the bottom electrode. A top electrode overlies the data storage layer. A conductive bridge is selectively formable within the data storage layer to couple the bottom electrode to the top electrode. A diffusion barrier layer is disposed between the data storage layer and the top electrode.
1. A memory device comprising:
a substrate;
a bottom electrode overlying the substrate;
a data storage layer overlying the bottom electrode, wherein the bottom electrode directly contacts the data storage layer;
a top electrode overlying the data storage layer, wherein a conductive bridge is selectively formable within the data storage layer to couple the bottom electrode to the top electrode, wherein a thickness of the top electrode is greater than a thickness of the data storage layer; and
a diffusion barrier layer disposed between the data storage layer and the top electrode, wherein sidewalls of the diffusion barrier layer are aligned with sidewalls of the bottom electrode.
2. The memory device of claim 1 , wherein the top electrode comprises a diffusive species, wherein the diffusion barrier layer is configured to prevent diffusion of the diffusive species from the top electrode to the data storage layer.
3. The memory device of claim 2 , wherein the diffusion barrier layer is substantially free of the diffusive species, and wherein the diffusive species is titanium.
4. The memory device of claim 1 , further comprising:
an active metal layer disposed between the data storage layer and the top electrode, wherein the active metal layer comprises a first conductive material and the diffusion barrier layer comprises a second conductive material different than the first conductive material.
5. The memory device of claim 4 , wherein the diffusion barrier layer is disposed between the data storage layer and the active metal layer.
6. The memory device of claim 5 , further comprising:
an upper diffusion barrier layer disposed between the active metal layer and the top electrode, wherein the upper diffusion barrier layer comprises the second conductive material.
7. The memory device of claim 4 , wherein the diffusion barrier layer is disposed between the active metal layer and the top electrode.
8. The memory device of claim 1 , wherein grain sizes of the diffusion barrier layer are smaller than grain sizes of the top electrode.
9. The memory device of claim 1 , wherein sidewalls of the top electrode, sidewalls of the data storage layer, and the sidewalls of the diffusion barrier layer are respectively aligned.
10. An integrated chip comprising:
a substrate;
a bottom electrode via overlying the substrate; and
a memory cell overlying the bottom electrode via, wherein the memory cell comprises a top electrode, a data storage layer, an active metal layer, and a diffusion barrier layer, wherein the top electrode comprises a diffusive species, wherein the active metal layer is disposed between the top electrode and the data storage layer, wherein the diffusion barrier layer underlies the top electrode and is configured to prevent diffusion of the diffusive species to the data storage layer, wherein the active metal layer comprises a first material and the diffusion barrier layer comprises a second material different than the first material, and wherein the first and second materials are conductive and different than the diffusive species.
11. The integrated chip of claim 10 , wherein the diffusive species is titanium, wherein the second material comprises ruthenium, tungsten, or iridium.
12. The integrated chip of claim 10 , wherein a bottom surface of the diffusion barrier layer directly contacts a top surface of the data storage layer, wherein a top surface of the diffusion barrier layer directly contacts a bottom surface of the active metal layer.
13. The integrated chip of claim 10 , wherein a bottom surface of the diffusion barrier layer directly contacts a top surface of the active metal layer, wherein a top surface of the diffusion barrier layer directly contacts a bottom surface of the top electrode.
14. The integrated chip of claim 10 , wherein a thickness of the active metal layer is greater than a thickness of the top electrode, and wherein the thickness of the top electrode is greater than a thickness of the data storage layer.
15. The integrated chip of claim 10 , wherein the diffusion barrier layer and the active metal layer are respectively substantially free of the diffusive species.
16. The integrated chip of claim 10 , wherein the bottom electrode via is spaced laterally between sidewalls of the memory cell.
17. The integrated chip of claim 10 , wherein a thickness of the diffusion barrier layer is less than a thickness of the active metal layer.
18. An integrated chip comprising:
a lower conductive wire overlying a substrate; and
a memory cell overlying the lower conductive wire, wherein the memory cell comprises a data storage layer, a top electrode over the data storage layer, a metal layer disposed between the data storage layer and the top electrode, and a diffusion barrier layer in direct contact with the metal layer, wherein a conductive bridge is formable and erasable within the data storage layer, wherein the diffusion barrier layer comprises a conductive material different than conductive materials of the top electrode and metal layer, and wherein grain sizes of the diffusion barrier layer are smaller than grain sizes of the top electrode.
19. The integrated chip of claim 18 , wherein the metal layer is electrochemically active.
20. The integrated chip of claim 18 , wherein the top electrode has a lower reactivity to oxygen than the metal layer.