Arithmetic operation circuit
View Patent ↗An artificial intelligence system includes a neural network layer including an arithmetic operation circuit that performs an arithmetic operation of a sigmoid function. The arithmetic operation circuit includes a first circuit configured to perform an exponent arithmetic operation using a Napier's constant e as a base and output a first calculation result when an exponent in the exponent arithmetic operation is a negative number, wherein an absolute value of the exponent is used in the exponent arithmetic operation, and a second circuit configured to subtract the first calculation result obtained by the first circuit from 1 and output the subtracted value.
1. An arithmetic operation system comprising: a neural network layer including an arithmetic operation circuit that performs an arithmetic operation of a sigmoid function, the arithmetic operation circuit comprising:
a multiplier circuit configured to perform multiplication of an input value that is input to the arithmetic operation circuit with a constant, and output a first calculation result of the multiplication;
a power and square root extraction arithmetic operator circuit configured to perform an exponent arithmetic operation using a Napier's constant e as a base and using the first calculation result as an exponent in the exponent arithmetic operation, and output a second calculation result of the exponent arithmetic operation;
an adder and divider circuit configured to perform addition of the second calculation result with 1 to output an added value and division of 1 by the added value to output a third calculation result of the addition and division;
a subtractor circuit configured to subtract the third calculation result from 1 and output a subtracted value as a fourth calculation result;
and a multiplexer configured to output the third calculation result as an output result of the sigmoid function when the input value is a negative number and output the fourth calculation result as the output result of the sigmoid function when the input value is a positive number.
2. The arithmetic operation system according to claim 1 , wherein the multiplexer is configured to receive the third calculation result at a first input terminal, the fourth calculation result at a second input terminal, and output one of the received third calculation result and the received fourth calculation result based on a selection signal received at a third input terminal.
3. The arithmetic operation system according to claim 2 , wherein the multiplexer outputs the received third calculation result as the output result of the sigmoid function when the selection signal indicates that the input value is a negative number, and outputs the fourth calculation result as the output result of the sigmoid function when the selection signal indicates that the input value is a positive number.
4. The arithmetic operation system according to claim 3 , further comprising:
a second multiplexer configured to output 1 as the output result of the sigmoid function when the input value is equal to or greater than a first value.
5. The arithmetic operation system according to claim 4 , further comprising:
a third multiplexer configured to output 0 as the output result of the sigmoid function when the input value is equal to or less than a second value.
6. An arithmetic operation system comprising: a neural network layer including an arithmetic operation circuit that performs an arithmetic operation of a sigmoid function, the arithmetic operation circuit comprising: a multiplier circuit configured to perform multiplication of an input value that is input to the arithmetic operation circuit with a constant, and output a first calculation result of the multiplication;
a power and square root extraction arithmetic operator circuit configured to perform an exponent arithmetic operation using 2 as a base and using the first calculation result a as an exponent in the exponent arithmetic operation, and output a second calculation result of the exponent arithmetic operation;
an adder and divider circuit configured to perform addition of the second calculation result with 1 to output an added value and division of 1 by the added value to output a third calculation result of the addition and division;
a subtractor circuit configured to subtract the third calculation result from 1 and output a subtracted value as a fourth calculation result;
and a multiplexer configured to output the third calculation result as an output result of the sigmoid function when the input value is a negative number and output the fourth calculation result as the output result of the sigmoid function when the input value is a positive number.
7. The arithmetic operation system according to claim 6 , wherein the multiplexer is configured to receive the third calculation result at a first input terminal, the fourth calculation result at a second input terminal, and output one of the received third calculation result and the received fourth calculation result based on a selection signal received at a third input terminal.
8. The arithmetic operation system according to claim 7 , wherein the multiplexer outputs the received third calculation result as the output result of the sigmoid function when the selection signal indicates that the input value is a negative number, and outputs the fourth calculation result as the output result of the sigmoid function when the selection signal indicates that the input value is a positive number.
9. The arithmetic operation system according to claim 8 , further comprising:
a second multiplexer configured to output 1 as the output result of the sigmoid function when the input value is equal to or greater than a first value.
10. The arithmetic operation system according to claim 9 , further comprising:
a third multiplexer configured to output 0 as the output result of the sigmoid function when the input value is equal to or less than a second value.