Page buffer and memory device including the same

1. A memory device, comprising:

a first page buffer supplying a first bias voltage to a selected bitline in a bitline precharge phase; and

a second page buffer supplying a second bias voltage to an unselected bitline, adjacent to the selected bitline, in the bitline precharge phase,

wherein the first page buffer includes a first bitline precharge circuit supplying the first bias voltage to the selected bitline, the second page buffer includes a second bitline precharge circuit supplying the second bias voltage to the unselected bitline,

wherein the second page buffer floats the unselected bitline in a sensing phase for detecting data of a selected memory cell connected to the selected bitline.

2. The memory device of claim 1 , wherein:

the second page buffer includes a bitline voltage control element for controlling the unselected bitline to be precharged with the second bias voltage, and

the bitline voltage control element is turned-on in the bitline precharge phase, and turned-off in the sensing phase.

3. The memory device of claim 2 , wherein:

the first page buffer includes a bitline current control element to controlling a current flowing into the selected bitline such that the selected bitline is precharged with a voltage lower than the first bias voltage, and

the memory device controls the bitline voltage control element using a control signal controlling the bitline current control element.

4. The memory device of claim 3 , wherein:

the memory device receives a control signal for controlling the bitline current control element in the sensing phase, and comparing the control signal with a reference signal,

the bitline voltage control element is turned-off during a time period in which the control signal is smaller than the reference signal,

the control signal includes a noise, and

a voltage of the selected bitline is changed according to the noise during a time period in which the control signal is smaller than the reference signal.

5. The memory device of claim 3 , wherein:

the memory device receives a control signal for controlling the bitline current control element in the sensing phase, and comparing the control signal with a reference signal,

the bitline voltage control element is turned-off during a time period in which the control signal is greater than the reference signal,

the control signal includes a noise, and

a voltage of the selected bitline is changed according to the noise during a time period in which the control signal is greater than the reference signal.

6. The memory device of claim 2 , wherein:

a control signal for controlling the bitline voltage control element is output in synchronization with a clock signal, and

timing at which the bitline voltage control element is turned-off is controlled in response to the clock signal.

7. The memory device of claim 2 , wherein a rising slope and a falling slope of a control signal for controlling the bitline voltage control element are controlled to control timing at which the bitline voltage control element is turned-off.

8. The memory device of claim 1 , wherein a capacitance value between the selected bitline and the unselected bitline is controlled in the sensing phase.

9. A page buffer, supplying a bitline voltage to a bitline connected to a plurality of memory cells, the page buffer comprising:

a data latch storing information on whether a selected memory cell is provided among the plurality of memory cells; and

a bitline precharge circuit, controlled by the data latch, and having a first bitline precharge control element connected between the bitline and a first power node for outputting a first bitline voltage, a second bitline precharge control element connected to a second power node for outputting a second bitline voltage lower than the first bitline voltage, and a first bitline voltage control element connected between the first bitline precharge control element and the second bitline precharge control element,

wherein the first bitline voltage control element is turned-off during a sensing node development phase when the bitline is an unselected bitline.

10. The page buffer of claim 9 , wherein the bitline precharge circuit further includes a bitline current control element controlling a current flowing into the bitline such that the bitline is precharged with a first bias voltage higher than a ground voltage and lower than a power supply voltage.

11. The page buffer of claim 10 , further comprising:

a sensing control element controlling connection between a sensing node and the bitline in a sensing phase for detecting data of a memory cell connected to the bitline.

12. The page buffer of claim 11 , wherein the page buffer further includes a second bitline voltage control element between the first bitline precharge control element and the bitline current control element, and

the second bitline voltage control element maintains a voltage between the bitline current control element and the sensing control element lower than a voltage of the sensing node in the sensing phase.

13. The page buffer of claim 11 , wherein the sensing control element is turned-on in a sensing node precharge phase, and maintains a turned-on state in the sensing phase.

14. The page buffer of claim 10 , wherein the bitline current control element is turned-on in a bitline precharge phase, is turned-off in a sensing node precharge phase, and is turned-on in a sensing node development phase.

15. A memory device, comprising:

a memory controller providing a first phase for bitline precharge, a second phase for sensing node precharge following the bitline precharge, and a third phase for sensing node development following the sensing node precharge;

a plurality of memory cells arranged in a stacked three-dimensional matrix of adjacent strings; and

at least one page buffer connected to the memory controller and the plurality of memory cells, the at least one page buffer including first and second non-grounded bitline bias voltage outputs concurrently connectable to adjacent strings, the at least one page buffer comprising a first page buffer bitline precharge circuit connected to a selected bitline with a first bias voltage during the first phase, and a second page buffer bitline precharge circuit connected to an unselected bitline, adjacent to the selected bitline, with a second bias voltage lower than the first bias voltage during the first phase,

wherein, during the second phase after the first phase, the first page buffer bitline precharge circuit precharges a sensing node connected to the selected bitline with a third bias voltage higher than the first bias voltage,

wherein during the third phase, the second page buffer bitline precharge circuit floats the unselected bitline while detecting data of a selected memory cell connected to the selected bitline,

wherein the first page buffer bitline precharge circuit includes a bitline current control element controlling a current flowing into the selected bitline such that the selected bitline is precharged with the first bias voltage,

wherein the memory device compares a control signal for controlling the bitline current control element with a reference signal during the third phase, and floats the unselected bitline during a time period in which the control signal is greater than the reference signal.

16. The memory device of claim 15 , wherein the control signal includes noise, and a voltage of the selected bitline is changed according to the noise during a time period in which the control signal is greater than the reference signal.

17. The memory device of claim 15 , wherein:

the at least one page buffer includes a bitline voltage control element controlling supply of the second bias voltage to the unselected bitline,

a turned-off state of the bitline voltage control element is maintained, during at least a portion of the third phase,

during the second phase, the bitline voltage control element is turned-off, and after the third phase ends, the bitline voltage control element is turned-one.

18. The memory device of claim 15 , wherein:

during the second phase, the bitline voltage control element is turned-off, and

before the third hate ends, the bitline voltage control element is turned-on.

19. The memory device of claim 15 , wherein:

after the third phase begins, the bitline voltage control element is turned-off, and

after the third phase ends, the bitline voltage control element is turned on.

20. The memory device of claim 15 , further comprising:

a sensing node circuit connected to each of the first page buffer bitline precharge circuit and the second page buffer bitline precharge circuit, respectively;

a data latch circuit connected to each of the first page buffer bitline precharge circuit and the second page buffer bitline precharge circuit, respectively;

a digital circuit with a bitline ground output connected to the at least one page buffer; and

an analog circuit with a bitline current control signal output connected to the at least one page buffer.