Superconducting qubit devices based on metal silicides

1. A qubit device for use in a quantum computing environment, the qubit device comprising:

a semiconductor substrate;

an insulating layer disposed on at least a portion of an upper surface of the substrate; and

a transition metal silicide (TMSi) heterojunction disposed on at least a portion of an upper surface of the insulating layer, the TMSi heterojunction comprising a link layer and at least first and second TMSi regions coupled with the link layer.

2. The device of claim 1 , wherein the first and second TMSi regions and the link layer in the heterojunction are disposed on the upper surface of the insulating layer, and the first and second TMSi regions are disposed on laterally opposing ends of the link layer, such that the heterojunction is configured having vertical interfaces between the link layer and the first and second TMSi regions.

3. The device of claim 2 , wherein the link layer and the first and second TMSi regions collectively align and form a congruent layer disposed on the upper surface of the insulating layer.

4. The device of claim 1 , wherein the first and second TMSi regions are disposed on an upper surface of corresponding portions of the link layer in the heterojunction, and the first and second TMSi regions are spaced laterally from one another by an opening formed therebetween, such that the heterojunction is configured having horizontal interfaces between the link layer and the first and second TMSi regions.

5. The device of claim 1 , wherein the link layer is a weak link layer comprising at least one of intrinsic and doped silicon.

6. The device of claim 1 , wherein the heterojunction comprises a vertical interface between the link layer and the first and second TMSi regions, the insulating layer is a gate oxide layer, the first and second TMSi regions are disposed on at least a portion of the upper of the gate oxide layer, and the link layer is a weak link layer comprising intrinsic or doped silicon which forms at least a portion of a channel disposed between the first and second TMSi regions.

7. The device of claim 1 , wherein each of the first and second TMSi regions in the heterojunction comprises a superconducting TMSi and the link layer comprises a superconducting silicon semiconductor.

8. The device of claim 1 , wherein an interface between the link layer and the first and second TMSi regions in the heterojunction is lattice-matched.

9. The device of claim 1 , wherein an interface between the link layer and the first and second TMSi regions in the heterojunction is atomically smooth.

10. The device of claim 1 , wherein the link layer forms at least a portion of a channel comprising intrinsic or doped silicon, the device further comprising:

a gate dielectric layer disposed on a portion of an upper surface of the heterojunction between the first and second TMSi regions and above the channel; and

a gate electrode disposed on an upper surface of the gate dielectric layer.

11. The device of claim 1 , wherein the link layer comprises one of a normal conductor, thereby forming a superconductor-normal conductor-superconductor (SNS) junction, and a geometric constriction, thereby forming a superconductor-geometric constriction-superconductor (ScS) junction.

12. The device of claim 1 , wherein the link layer comprises at least one of intrinsic silicon and doped silicon.

13. A method of forming a qubit structure for use in a quantum computing environment, the method comprising:

forming an insulating layer on at least a portion of an upper surface of a semiconductor substrate; and

forming a transition metal silicide (TMSi) heterojunction on at least a portion of an upper surface of the insulating layer, the TMSi heterojunction comprising a link layer and at least first and second TMSi regions coupled with the link layer.

14. The method of claim 13 , wherein forming the TMSi heterojunction comprises:

fainting a silicon layer on a portion of the upper surface of the insulating layer, the silicon layer serving as the link layer of the TMSi heterojunction; and

forming the first and second TMSi regions on respective portions of the upper surface of the insulating layer, first and second TMSi regions being disposed on laterally opposing ends of the silicon layer, such that the heterojunction is configured having vertical interfaces between the link layer and the first and second TMSi regions.

15. The method of claim 14 , wherein the first and second TMSi regions and the silicon layer are formed in a same plane on the upper surface of the insulating layer.

16. The method of claim 13 , wherein the link layer and the first and second TMSi regions collectively align and form a congruent layer disposed on the upper surface of the insulating layer.

17. The method of claim 13 , wherein forming the TMSi heterojunction comprises:

forming a silicon layer on the upper surface of the insulating layer, the silicon layer serving as the link layer of the TMSi heterojunction;

forming a TMSi layer on an upper surface of the silicon layer; and

forming a trench through the TMSi layer through which a portion of the underlying silicon layer is exposed, the trench dissecting the TMSi layer so as to form the first and second TMSi regions spaced laterally from one another by the trench, such that the TMSi heterojunction is configured having horizontal interfaces between the silicon layer and the first and second TMSi regions.

18. The method of claim 17 , further comprising filling the trench with an insulating material.

19. The method of claim 13 , wherein each of the first and second TMSi regions in the heterojunction comprises a superconducting TMSi and the link layer comprises a superconducting silicon semiconductor.

20. The method of claim 13 , wherein the link layer forms at least a portion of a channel comprising intrinsic or doped silicon, the method further comprising:

forming a gate dielectric layer on a portion of an upper surface of the heterojunction between the first and second TMSi regions and above the channel; and

forming a gate electrode on an upper surface of the gate dielectric layer.