Calibration circuit and associated calibrating method capable of precisely adjusting clocks with distorted duty cycles and phases
A calibration circuit, including a duty cycle correction circuit and a phase correction circuit and associated calibrating method, are provided. Firstly, a first duty cycle adjusted clock and a second duty cycle adjusted clock are generated by the duty cycle correction circuit based on a first input clock and a second input clock, respectively. Then, a first delay adjusted clock and a second delay adjusted clock are generated by the phase correction circuit based on a phase of the first duty cycle adjusted clock, and a detection signal is generated. The detection signal is related to a duty cycle of the first input clock, a duty cycle of the second input clock, and a phase difference between the second delay adjusted clock and the first delay adjusted clock. Later, the duty cycle correction circuit and the phase correction circuit are controlled in response to the detection signal.
1. A calibration circuit, comprising:
a duty cycle correction circuit, configured for generating a first duty cycle adjusted clock based on a first input clock, and generating a second duty cycle adjusted clock based on a second input clock, wherein frequency of the first input clock and frequency of the second input clock are equivalent;
a phase correction circuit, electrically connected to the duty cycle correction circuit, configured for generating a first delay adjusted clock based on a phase of the first duty cycle adjusted clock, and generating a second delay adjusted clock based on a phase of the second duty cycle adjusted clock;
a clock selection circuit, electrically connected to the phase correction circuit, comprising:
a first clock selector, configured for outputting a first selected signal based on a first feedback clock, wherein the first feedback clock is generated from the first delay adjusted clock;
a comparison circuit, electrically connected to the first clock selector, configured for generating a comparison signal based on a second feedback clock and the first selected signal, wherein the second feedback clock is generated from the second delay adjusted clock; and
a second clock selector, electrically connected to the comparison circuit, configured for outputting a second selected signal based on the second feedback clock, the comparison signal, and the first selected signal, wherein the second selected signal is related to generation of a detection signal, wherein the detection signal is related to a duty cycle of the first input clock, a duty cycle of the second input clock, and a phase difference between the second delay adjusted clock and the first delay adjusted clock; and
a first control circuit, electrically connected to the duty cycle correction circuit, the phase correction circuit, and the clock selection circuit, configured for controlling the duty cycle correction circuit and the phase correction circuit in response to the detection signal.
2. The calibrating circuit according to claim 1 , wherein
the first input clock is related to a recovered data clock, and the second input clock is related to a recovered edge clock.
3. The calibration circuit according to claim 1 , wherein the first control circuit transmits a first duty cycle control signal and a second duty cycle control signal to the duty cycle correction circuit, and the duty cycle correction circuit comprises:
a first duty cycle corrector, electrically connected to the first control circuit, configured for receiving the first input clock and the first duty cycle control signal, and generating the first duty cycle adjusted clock, wherein a duty cycle of the first duty cycle adjusted clock is adjusted in response to the first duty cycle control signal; and
a second duty cycle corrector, electrically connected to the first control circuit, configured for receiving the second input clock and a second duty cycle control signal, and generating the second duty cycle adjusted clock, wherein a duty cycle of the second duty cycle adjusted clock is adjusted in response to the second duty cycle control signal.
4. The calibration circuit according to claim 3 , wherein the first control circuit transmits a first phase control signal and a second phase control signal to the phase correction circuit, and the phase correction circuit comprises:
a first delay circuit, electrically connected to the first duty cycle corrector and the first control circuit, configured for receiving the first duty cycle adjusted clock and the first phase control signal, and generating the first delay adjusted clock, wherein a phase of the first delay adjusted clock is adjusted based on the first phase control signal; and
a second delay circuit, electrically connected to the second duty cycle corrector and the first control circuit, configured for receiving the second duty cycle adjusted clock and the second phase control signal, and generating the second delay adjusted clock, wherein a phase of the second delay adjusted clock is adjusted based on the second phase control signal.
5. The calibration circuit according to claim 4 , further comprises:
a duty cycle detector, electrically connected to the second clock selector, and the first control circuit, configured for generating the detection signal according to a duty cycle of the second selected signal.
6. The calibration circuit according to claim 5 , wherein the first control circuit generates the first duty cycle control signal according to the detection signal when the first feedback clock is selected as an input of the first clock selector, and the first selected signal is selected as an input of the second clock selector.
7. The calibration circuit according to claim 5 , wherein the first control circuit generates the second duty cycle control signal according to the detection signal when the second feedback clock is selected as an input of the second clock selector.
8. The calibration circuit according to claim 5 , wherein the first control circuit generates at least one of the first phase control signal and the second phase control signal according to the detection signal when the first feedback clock is selected as an input of the first clock selector, and the comparison signal is selected as an input of the second clock selector.
9. The calibration circuit according to claim 8 , wherein
a duty cycle of the comparison signal is shorter than 50% when the phase difference between the second feedback clock and the first feedback clock is less than 90 degrees;
the duty cycle of the comparison signal is higher than 50% when the phase difference between the second feedback clock and the first feedback clock is greater than 90 degrees; and
the duty cycle of the comparison signal is equivalent to 50% when the phase difference between the second feedback clock and the first feedback clock is equivalent to 90 degrees.
10. The calibration circuit according to claim 9 , wherein the comparison signal is selected as the input of the second clock selector, wherein
the detection signal is equivalent to a first logic level when the duty cycle of the second selected signal is shorter than 50%;
the detection signal is equivalent to a second logic level when the duty cycle of the second selected signal is higher than 50%; and
the detection signal transits between the first logic level and the second logic level when the duty cycle of the second selected signal is equivalent to 50%.
11. The calibration circuit according to claim 1 , further comprising:
a phase interpolator, electrically connected to the duty cycle correction circuit, configured for receiving a third input clock and generating a phase interpolated error clock based on a phase interpolator code, wherein the phase interpolator code is set by a phase interpolation control signal, and the frequency of the first input clock and frequency of the third input clock are equivalent; and
a second control circuit, electrically connected to the phase correction circuit, the clock selection circuit, and the phase interpolator, configured for generating the phase interpolation control signal based on the second feedback clock and a third feedback clock, wherein the third feedback clock is generated from a third delay adjusted clock.
12. The calibration circuit according to claim 11 , wherein the duty cycle correction circuit further comprises a third duty cycle corrector, and the phase correction circuit further comprises a third delay circuit, wherein
the third duty cycle corrector and the third delay circuit are electrically connected to the first control circuit, and
the third delay circuit is electrically connected to the clock selection circuit, the second control circuit, and the third duty cycle corrector.
13. The calibration circuit according to claim 12 , wherein
the third duty cycle corrector receives the phase interpolated error clock from the phase interpolator and a third duty cycle control signal from the first control circuit and generates a third duty cycle adjusted clock, wherein a duty cycle of the third duty cycle adjusted clock is adjusted in response to the third duty cycle control signal; and
the third delay circuit receives the third duty cycle adjusted clock from the third duty cycle corrector and a third phase control signal from the first control circuit, and generates the third delay adjusted clock, wherein a phase of the third delay adjusted clock is adjusted based on the third phase control signal.
14. The calibration circuit according to claim 13 , wherein the first control circuit generates the third duty cycle control signal according to the detection signal when the third feedback clock is selected as an input of the first clock selector, and the first selected signal is selected as an input of the second clock selector.
15. The calibration circuit according to claim 13 , wherein
the first control circuit generates the third phase control signal according to the detection signal when the third feedback clock is selected as an input of the first clock selector, and the comparison signal is selected as an input of the second clock selector.
16. The calibration circuit according to claim 15 , wherein
a duty cycle of the comparison signal is equivalent to 50% when a phase difference between the second feedback clock and the third feedback clock is equivalent to 90 degrees;
the duty cycle of the comparison signal is shorter than 50% when the phase difference between the second feedback clock and the third feedback clock is less than 90 degrees; and
the duty cycle of the comparison signal is higher than 50% when the phase difference between the second feedback clock and the third feedback clock is greater than 90 degrees.
17. The calibration circuit according to claim 11 , wherein
the second control circuit continuously changes the phase interpolator code and samples a logic level of the second feedback clock with the third feedback clock;
the second control circuit records the phase interpolator code as a first phase interpolator value when the sampled logic level of the second feedback clock transits from a first logic level to a second logic level;
the second control circuit records the phase interpolator code as a second phase interpolator value when the sampled logic level of the second feedback clock transits from the second logic level to the first logic level; and
the second control circuit sets the phase interpolator code with a third phase interpolator value, wherein the third phase interpolator value is obtained based on the first phase interpolator value and the second phase interpolator value.
18. The calibration circuit according to claim 17 , wherein the third phase interpolator value is an average of the first phase interpolator value and the second phase interpolator value, wherein the first feedback clock is synchronized with the third feedback clock.
19. A calibrating method applied to a calibration circuit comprising
a duty cycle correction circuit and a phase correction circuit, comprising following steps:
generating a first duty cycle adjusted clock and a second duty cycle adjusted clock by the duty cycle correction circuit based on a first input clock and a second input clock, respectively, wherein frequency of the first input clock and frequency of the second input clock are equivalent;
generating a first delay adjusted clock and a second delay adjusted clock by the phase correction circuit based on a phase of the first duty cycle adjusted clock;
outputting a first selected signal based on a first feedback clock, wherein the first feedback clock is generated from the first delay adjusted clock;
generating a comparison signal based on a second feedback clock and the first selected signal, wherein the second feedback clock is generated from the second delay adjusted clock;
outputting a second selected signal based on the second feedback clock, the comparison signal, and the first selected signal;
generating a detection signal based on the second selected signal, wherein the detection signal is related to a duty cycle of the first input clock, a duty cycle of the second input clock, and a phase difference between the second delay adjusted clock and the first delay adjusted clock; and
controlling the duty cycle correction circuit and the phase correction circuit in response to the detection signal.
20. A calibration circuit, comprising:
a duty cycle correction circuit, configured for generating a first duty cycle adjusted clock based on a first input clock, and generating a second duty cycle adjusted clock based on a second input clock, wherein frequency of the first input clock and frequency of the second input clock are equivalent;
a phase correction circuit, electrically connected to the duty cycle correction circuit, configured for generating a first delay adjusted clock based on a phase of the first duty cycle adjusted clock, and generating a second delay adjusted clock based on a phase of the second duty cycle adjusted clock;
a sampling module, electrically connected to the phase correction circuit, configured for generating a first feedback clock based on the first delay adjusted clock, and generating a second feedback clock based on the second delay adjusted clock;
a clock selection circuit, electrically connected to the sampling module, configured for generating a detection signal based on the first feedback clock and the second feedback clock, wherein the detection signal is related to a duty cycle of the first input clock, a duty cycle of the second input clock, and a phase difference between the first feedback clock and the second feedback clock; and
a first control circuit, electrically connected to the duty cycle correction circuit, the phase correction circuit, and the clock selection circuit, configured for controlling the duty cycle correction circuit and the phase correction circuit in response to the detection signal.