IP Library Granted Patent US 10,996,870
Granted Patent B2
US 10,996,870 · App. 16/811,775 · Granted May 4, 2021

Deterministic read disturb counter-based data checking for NAND flash

Inventor: Neil Buxton (Berkshire, GB)
Assignee: Toshiba Memory Corporation
G06F3/0619G06F3/0655G06F3/0679G06F11/0727G06F11/0754G06F11/0793G11C16/3431G06F2201/81G11C16/0483
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Quick Facts
Patent No.
US 10,996,870
App. No.
16/811,775
Granted
May 4, 2021
Kind
B2
Abstract

A data storage device comprises a non-volatile semiconductor memory device and a solid-state drive controller communicatively coupled to the non-volatile semiconductor memory device. The non-volatile semiconductor memory device can store data in memory blocks. The solid-state drive controller can, periodically, retrieve counts from a counter table, select a predetermined number of memory blocks corresponding to the lowest counts, and determine an integrity of the stored data in each of the predetermined number of memory blocks. Each count can correspond to a difference between a count limit and a number of read operations performed on one of the memory blocks.

Claims (36)

1. An SSD comprising:

a non-volatile semiconductor memory device configured to store data in a plurality of memory blocks; and

a controller communicatively coupled to the non-volatile semiconductor memory device, configured to:

for each memory block of the plurality of memory blocks, determine a number of remaining read operations, if any, capable of being performed;

identify a first set of a plurality of memory blocks from the plurality of memory blocks, wherein each of the plurality of memory blocks in the first set has the number of remaining read operations capable of being performed less than the number of remaining read operations capable of being performed on each memory block that is not identified in the first set;

determine an error level of each memory block of the first set,

wherein, a number of memory blocks in the first set is less than a total number of memory blocks in the plurality of memory blocks and wherein the number of memory blocks in the first set is based on a predetermined criteria.

2. The SSD of claim 1 , wherein the predetermined criteria corresponds to a number of memory blocks with data with read disturb errors within a predetermined time period.

3. The SSD of claim 1 , wherein the predetermined criteria corresponds to a rate of arrival of read requests from a host communicatively coupled to the SSD.

4. The SSD of claim 1 , wherein predetermined criteria corresponds an average number of the plurality of memory blocks with an error level above a predetermined threshold.

5. The SSD of claim 1 , wherein the predetermined criteria is a fixed number.

6. The SSD of claim 1 , wherein the predetermined criteria corresponds to a size of each of a plurality of IO operations.

7. The SSD of claim 1 , wherein is the predetermined criteria corresponds to a page size of the memory blocks.

8. The SSD of claim 1 , wherein the predetermined criteria corresponds to a number of read operations received in a predetermined time period.

9. The SSD of claim 1 , wherein if the error level of a memory block of the first set satisfies a threshold, then:

read data stored in the memory block;

error correct the data read from the memory block; and

store the error corrected data in a second memory block.

10. The SSD of claim 1 , wherein if the error level of a memory block of the first set does not satisfy a threshold, the controller is further configured to increase the number of remaining read operations capable of being performed on the memory block to a predetermined number.

11. A method of managing an SSD, the method comprising:

determining a number of remaining read operations, if any, capable of being performed on each memory block of a plurality memory blocks;

identifying a first set of a plurality of memory blocks from the plurality of memory blocks, wherein each of the plurality of memory blocks in the first set has the number of remaining read operations capable of being performed less than the number of remaining read operations capable of being performed on each memory blocks that is not identified in the first set; and

determining the error level of each memory block of the first set,

wherein, a number of memory blocks in the first set is less than a total number of memory blocks in the plurality of memory blocks and the number of memory blocks in the first set is based on a predetermined criteria.

12. The method of claim 11 , wherein the predetermined criteria corresponds to a number of memory blocks with data with read disturbs errors within a predetermined time period.

13. The method of claim 11 , wherein the predetermined criteria corresponds to a rate of arrival of read requests from a host communicatively coupled to the SSD.

14. The method of claim 11 , wherein the predetermined criteria corresponds to an average number of the plurality of memory blocks with an error level above a predetermined threshold.

15. The method of claim 11 , wherein the predetermined criteria is a fixed number.

16. The method of claim 11 , wherein the predetermined criteria corresponds to a size of each of a plurality of TO operations.

17. The method of claim 11 , wherein is the predetermined criteria corresponds to a page size of the memory blocks.

18. The method of claim 11 , wherein the predetermined criteria corresponds to a number of read operations received in a predetermined time period.

19. The method of claim 11 , wherein if the error level of a memory block of the first set satisfies a threshold, then:

reading data stored in the memory block;

error correcting the data read from the memory block; and

storing the error corrected data in a second memory block.

20. The method of claim 11 , wherein if the error level of a memory block of the first set does not satisfy a threshold, increasing the number of remaining read operations capable of being performed on the memory block to a predetermined number.

Assignments (3)
CHANGE OF NAME AND ADDRESS Recorded Feb 4, 2022
From: K.K PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 058957/0124 →
CHANGE OF NAME AND ADDRESS Recorded Jan 31, 2022
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 058905/0582 →
MERGER Recorded Jan 31, 2022
From: TOSHIBA MEMORY CORPORATION
To: K.K PANGEA
Reel/Frame 058946/0675 →
Continuity (3)
Continuation 16186836 · Nov 12, 2018
Continuation 15702930 · Sep 13, 2017
Related Publication 20200278800A1 · Sep 3, 2020