Fault detection in hybrid DC-DC power convertors
There are disclosed fault detection circuits and methods for an N-to-1 Dickson topology hybrid DC-DC power converter. A short circuit fault detection circuit comprises: first and second measuring circuits configured to measure first and second voltages, Vsw 1 , Vsw 2 , at the switching node in the first and second state; first and second calculation circuits configured to calculate first and second absolute error voltage as an absolute difference of the respective first and second voltages in one operating cycle (Vsw 1 [n−1], Vsw 2 [n−1]) and in a next subsequent operating cycle (Vsw 1 [n], Vsw 2 [n]); and first and second fault circuits configured to provide first and second fault outputs indicative of a fault in response to the respective first or second absolute error voltage exceeding a short-circuit-trip level. Open circuit fault detection circuits and methods are also disclosed.
1. A fault detection circuit for a N-to-1 Dickson topology hybrid DC-DC power converter having at least (N−1) level-setting capacitors, an input terminal for receiving an input voltage, a ground terminal, and a switching node connected to an inductor, and operational according to an operating cycle comprising first, second and third states;
the fault detection circuit comprising:
a first measuring circuit configured to measure a first voltage, VSW 1 , at the switching node in the first state in which first and second sets of the level-setting capacitors are being charged and discharged;
a first calculation circuit configured to calculate a first error voltage as a difference of the first voltage in one operating cycle (VSW 1 [n−1]) and in a next subsequent operating cycle (VSW 1 [n]);
a first fault circuit configured to provide a first fault output indicative of a fault in response to an absolute value of the first error voltage exceeding a short-circuit-trip level;
a second measuring circuit configured to measure a second voltage, VSW 2 , at the switching node in the second state in which the first and second sets of the level-setting capacitors are being respectively discharged and charged;
a second calculation circuit configured to calculate a second error voltage as a difference of the second voltage in one operating cycle (VSW 2 [n−1] and in a next subsequent operating cycle (VSW 2 [n]); and
a second fault circuit configured to provide a second fault output indicative of a fault in response to an absolute value of the second error voltage exceeding the short-circuit-trip level.
2. The fault detection circuit as claimed in claim 1 , wherein the first and second calculation circuits, and the first and second fault circuits are digital circuits.
3. The fault detection circuit as claimed in claim 1 , further comprising:
a third measuring circuit configured to measure the input voltage;
a third calculation circuit configured to calculate a third error voltage as the value of: the sum of the first and the second voltage in one operating cycle minus 2/N times the input voltage; and
a third fault detection circuit configured to provide a third fault output indicative of a fault in response to an absolute value of the second error voltage exceeding an open-circuit-trip level.
4. The fault detection circuit as claimed in claim 3 , wherein the first, second and third calculation circuits, and the first, second and third fault circuits are digital circuits.
5. The fault detection circuit as claimed in claim 4 , further comprising a circuit providing a summary fault output in response to at least one of the first, second and third fault outputs being indicative of a fault.
6. The fault detection circuit as claimed in claim 4 , wherein each of the first, second and third measuring circuits comprise an analog-to-digital converter.
7. The fault detection circuit as claimed in claim 4 , wherein each of the first, second and third measuring circuits comprise the same analog-to-digital converter.
8. The fault detection circuit as claimed in claim 4 , wherein each of the first, second, and third fault detection circuits comprises a comparator.
9. The fault detection circuit as claimed in claim 8 , wherein each of the first and second fault detection circuits comprises the same comparator.
10. The fault detection circuit as claimed in claim 1 , wherein the first, second and third calculation circuits, and the first, second and third fault circuits are analog circuits.
11. The fault detection circuit as claimed in claim 1 , wherein N=4, the first set of level-setting capacitors comprises a first capacitor and a third capacitor, and the second set of level-setting capacitors comprises a second capacitor.
12. A method for programming a fault detection circuit to detect a fault in a N-to-1 Dickson topology hybrid DC-DC power converter having an operating cycle and having at least (N−1) level-setting capacitors, an input terminal for receiving an input voltage, a ground terminal, and a switching node connected to an inductor; the method comprising configuring the fault detection circuit for:
measuring a voltage at the switching node in first and second states in which first and second sets of level-setting capacitors are being charged and discharged, and discharged and charged, respectively;
calculating a first error voltage, using a first calculation circuit, as a difference of the voltage at the switching node in the first state in an operating cycle and a next subsequent operating cycle;
calculating a second error voltage, using a second calculation circuit, as a difference of the voltage at the switching node in the second state in an operating cycle and a next subsequent operating cycle;
comparing the sum of the voltages, using a third calculation circuit, at the switching node in first and second states with 2/N times the input voltage, to determine a third error voltage;
detecting a fault in response to either an absolute value of the third error voltage exceeding a first trip voltage level, or an absolute value of either the first or second error voltages exceeding a second trip voltage level.
13. The method of claim 12 ,
wherein in the first state a first set of capacitors is charged and a second set of capacitors is discharged such that in normal operation the switching node is 1/N times the voltage of the input terminal; wherein in the second state the first set of capacitors is discharged and the second set of capacitors is charged such that in normal operation the switching node is quarter 1/N times the voltage of the input terminal, and in the third state the switching node is short-circuited to the ground terminal; and wherein a cycle of normal operation comprises operating successively in the first, third, second and third states.
14. The method of claim 12 ,
wherein calculating a first absolute error voltage as an absolute difference of the voltage at the switching node in the first state in an operating cycle and a next subsequent operating cycle comprises:
subtracting the respective switching node voltage in the first and second states in the (n−1)th cycle (VSW 1 [n−1], VSW 2 [n−1]) to determine a first and a second absolute errors (Vsc 1 ,err, VSW 2 ,ERR), according to:
VSW 1 , ERR=|VSW 1 [ n ]− VSW 1 [ n− 1]|, and
VSW 2 , ERR=|VSW 2 [ n ]− VSW 2 [ n− 1]|.
15. The method of claim 12 ,
wherein comparing the sum of the voltages at the switching node in first and second states with 2/N times the input voltage, to determine a third absolute error voltage comprises:
summing the switching node voltage in the first and second states in the (n)th cycle to determine a sum value (Vsum[n]), according to
( V SUM[ n ]= VSW 1 [ n ]+ VSW 2 [ n ]), and
subtracting 2/N times the input voltage to determine a third absolute error (VSUM,ERR) according to:
V SUM, ERR=|V SUM[ n ]− VIN/ 2.
16. The method of claim 12 ,
wherein N=4, the first set of level-setting capacitors comprises a first capacitor and a third capacitor, and the second set of level-setting capacitors comprises a second capacitor.
17. An N-to-1 Dickson topology hybrid DC-DC power converter having at least (N−1) level-setting capacitors, an input terminal for receiving an input voltage, a ground terminal, and a switching node connected to an inductor, and operational according to an operating cycle comprising first, second and third states;
and fault detection circuit comprising:
a first measuring circuit configured to measure a first voltage, VSW 1 , at the switching node in the first state in which first and second sets of the level-setting capacitors are being charged and discharged;
a first calculation circuit configured to calculate a first error voltage as a difference of the first voltage in one operating cycle (VSW 1 [n−1]) and in a next subsequent operating cycle (VSW 1 [n]);
a first fault circuit configured to provide a first fault output indicative of a fault in response to an absolute value of the first error voltage exceeding a short-circuit-trip level;
a second measuring circuit configured to measure a second voltage, VSW 2 , at the switching node in the second state in which the first and second sets of the level-setting capacitors are being respectively discharged and charged;
a second calculation circuit configured to calculate a second error voltage as a difference of the second voltage in one operating cycle (VSW 2 [n−1] and in a next subsequent operating cycle (VSW 2 [n]); and
a second fault circuit configured to provide a second fault output indicative of a fault in response to an absolute value of the second error voltage exceeding the short-circuit-trip level.
18. The N-to-1 Dickson topology hybrid DC-DC power converter of claim 17 , wherein the fault detection circuit further comprises:
a third measuring circuit configured to measure the input voltage;
a third calculation circuit configured to calculate a third error voltage as the value of: the sum of the first and the second voltage in one operating cycle minus 2/N times the input voltage; and
a third fault detection circuit configured to provide a third fault output indicative of a fault in response to an absolute value of the second error voltage exceeding an open-circuit-trip level.