IP Library › Granted Patent US 11,594,514
Granted Patent B2
US 11,594,514 · App. 16/816,571 · Granted Feb 28, 2023

Semiconductor device and method of manufacturing the same

Inventors: Kazuhiro Nakanishi (Yokkaichi, JP); Shigehiro Yamakita (Yokkaichi, JP); Kazuhiro Nojima (Mie, JP); Kenichi Kadota (Yokkaichi, JP)
Assignee: Kioxia Corporation
H01L24/89H01L24/05H01L24/08H01L2224/05026H01L2224/05563H01L2224/08147H01L2224/80895H01L2224/80896
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Quick Facts
Patent No.
US 11,594,514
App. No.
16/816,571
Granted
Feb 28, 2023
Kind
B2
Abstract

In one embodiment, a semiconductor device includes a substrate, a lower pad provided above the substrate, and an upper pad provided on the lower pad. The lower pad includes a first pad and a plurality of first connection portions provided on the first pad, and the upper pad is provided on the plurality of first connection portions, or the upper pad includes a second pad and a plurality of second connection portions provided under the second pad, and the lower pad is provided under the plurality of second connection portions.

Claims (22)

1. A semiconductor device, comprising:

a first chip including a first interconnect layer;

a second chip bonded to the first chip, and including a second interconnect layer; and

a metal pad provided on a bonding face of the first chip and the second chip and electrically connecting a first interconnect in the first interconnect layer to a second interconnect in the second interconnect layer,

wherein the metal pad includes a first portion provided in the first chip,

the first portion includes a first pad, and a plurality of first connection portions provided directly on and above the first pad,

one of the plurality of first connection portions includes a first metal body and a first barrier metal layer covering a part of an outer periphery of the first metal body, and

the first metal body of one of the plurality of first connection portions is in contact with the first pad via the first barrier metal layer.

2. The device of claim 1 , wherein the metal pad further includes a second portion provided on the first portion in the first chip,

the second portion includes a second pad, and a plurality of second connection portions provided directly on and under the second pad,

one of the plurality of second connection portions includes a second metal body and a second barrier metal layer covering a part of an outer periphery of the second metal body, and

the second metal body of one of the plurality of second connection portions is in contact with the second pad via the second barrier metal layer.

3. The device of claim 2 , wherein a number of the second connection portions is equal to a number of the first connection portions.

4. The device of claim 1 , wherein

the metal pad further includes a third pad provided on the plurality of first connection portions and under the plurality of second connection portions.

5. The device of claim 4 , wherein the metal pad further includes a fourth pad provided on the third pad and under the plurality of second connection portions.

6. The device of claim 5 , wherein a number of the second connection portions is equal to a number of the first connection portions.

7. The device of claim 4 , wherein the third pad is provided on the first connection portions via no barrier metal layer.

8. The device of claim 5 , wherein the fourth pad is provided on the third pad via no barrier metal layer.

9. The device of claim 1 , wherein

the first pad is provided in the first interconnect layer, or

the second pad is provided in the second interconnect layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 12, 2020
From: NAKANISHI, KAZUHIRO; YAMAKITA, SHIGEHIRO; NOJIMA, KAZUHIRO; KADOTA, KENICHI
To: KIOXIA CORPORATION
Reel/Frame 052096/0199 →
Priority Claims (1)
JP JP2019-153110 · Aug 23, 2019 · national
Continuity (1)
Related Publication 20210057376A1 · Feb 25, 2021