Dynamic control of memory bandwidth allocation for a processor

1. An apparatus comprising:

a plurality of processor cores;

first circuitry, coupled to the plurality of processor cores, to apply at least one of a plurality of memory bandwidth settings to the plurality of processor cores to dynamically adjust priorities of memory bandwidth allocated for one or more workloads to be processed by the plurality of processor cores;

a memory controller, coupled to the plurality of processor cores, the memory controller including a performance monitor to generate performance monitoring statistics by monitoring performance of the one or more workloads by the plurality of processor cores based at least in part on performance monitoring configuration parameters; and

second circuitry, coupled to the first circuitry and the memory controller, to set the performance monitoring configuration parameters based at least in part on memory class of service parameters, and to set the memory bandwidth settings based at least in part on the performance monitoring statistics received from the performance monitor.

2. The apparatus of claim 1 , wherein the second circuitry comprises:

a controller to calculate an error value as a difference between a set point and a process variable of the performance monitoring statistics based on proportional-integral-derivative (PID) control; and

third circuitry to generate the memory bandwidth settings based at least in part on the error value.

3. The apparatus of claim 1 , wherein one or more of the plurality of memory bandwidth settings comprises a first value for memory bandwidth allocation for a low priority processor core based on an assigned memory class of service of the low priority processor core.

4. The apparatus of claim 3 , wherein one or more of the plurality of memory bandwidth settings comprises a second value for memory bandwidth allocation for a high priority processor core based on an assigned memory class of service of the high priority processor core, the first value being less than the second value.

5. The apparatus of claim 1 , wherein a class of service of one of the plurality of processor cores corresponds to one of the memory class of service parameters.

6. The apparatus of claim 2 , wherein the performance monitoring configuration parameters comprise the set point, a time window, a plurality of events, and a plurality of enable bits corresponding to the plurality of events.

7. The apparatus of claim 1 , wherein the memory class of service parameters comprise a plurality of sets of parameters, and at least one set for a selected memory class of service including one or more of: a priority, a minimum delay value, and maximum delay value, and an identifier of the selected memory class of service.

8. A system comprising:

first circuitry to set memory class of service parameters; and

processor circuitry, the processor circuitry including

a plurality of processor cores;

second circuitry, coupled to the plurality of processor cores, to apply memory bandwidth settings to the plurality of processor cores to dynamically adjust priorities of memory bandwidth allocated for one or more workloads to be processed by the plurality of processor cores;

a memory controller, coupled to the plurality of processor cores, the memory controller including a performance monitor to generate performance monitoring statistics by monitoring performance of the one or more workloads by the plurality of processor cores based at least in part on performance monitoring configuration parameters; and

third circuitry, to set the performance monitoring configuration parameters based at least in part on the memory class of service parameters, and to set the memory bandwidth settings based at least in part on the performance monitoring statistics received from the performance monitor.

9. The system of claim 8 , wherein the third circuitry comprises:

a controller to calculate an error value as a difference between a set point and a process variable of the performance monitoring statistics based on proportional-integral-derivative (PID) control; and

fourth circuitry to generate the memory bandwidth settings based at least in part on the error value.

10. The system of claim 8 , wherein one or more of the plurality of bandwidth settings comprises a first value for memory bandwidth allocation for a low priority processor core based on an assigned memory class of service of the low priority processor core.

11. The system of claim 10 , wherein one or more of the plurality of memory bandwidth settings comprises a second value for memory bandwidth allocation for a high priority processor core based on an assigned memory class of service of the high priority processor core, the first value being less than the second value.

12. The system of claim 8 , wherein a class of service of one of the plurality of processor cores corresponds to one of the memory class of service parameters.

13. The system of claim 9 , wherein the performance monitoring configuration parameters comprise the set point, a time window, a plurality of events, and a plurality of enable bits corresponding to the plurality of events.

14. The system of claim 8 , wherein the memory class of service parameters comprise a plurality of sets of parameters, and at least one set for a selected memory class of service including one or more of: a priority, a minimum delay value, and maximum delay value, and an identifier of the selected memory class of service.

15. A method comprising:

receiving memory class of service parameters;

setting performance monitoring configuration parameters, based at least in part on the memory class of service parameters, for use by a performance monitor of a memory controller to generate performance monitoring statistics by monitoring performance of one or more workloads by a plurality of processor cores based at least in part on the performance monitoring configuration parameters;

receiving the performance monitoring statistics from the performance monitor; and

generating, based at least in part on the performance monitoring statistics, a plurality of memory bandwidth settings to be applied to the plurality of processor cores to dynamically adjust priorities of memory bandwidth allocated for the one or more workloads to be processed by the plurality of processor cores.

16. The method of claim 15 , comprising periodically repeating receiving the performance monitoring statistics from the performance monitor and generating the plurality of memory bandwidth settings to be applied to the plurality of processor cores to dynamically adjust priorities of memory bandwidth allocated for the one or more workloads to be processed by the plurality of processor cores.

17. The method of claim 15 , wherein generating the plurality of memory bandwidth settings comprises calculating an error value as a difference between a set point and a process variable of the performance monitoring statistics and generating the memory bandwidth settings based at least in part on the error value.

18. The method of claim 15 , wherein the performance monitoring configuration parameters comprise a set point, a time window, a plurality of events, and a plurality of enable bits corresponding to the plurality of events.

19. The method of claim 15 , wherein the memory class of service parameters comprise a plurality of sets of parameters, and at least one set for a selected memory class of service including one or more of: a priority, a minimum delay value, and maximum delay value, and an identifier of the selected memory class of service.

20. The method of claim 19 , wherein generating the plurality of memory bandwidth settings comprises determining a delay budget and setting at least one of the plurality of memory bandwidth settings to a delay value based at least in part on the delay budget and the priority of the selected memory class of service.

21. A method comprising:

receiving memory class of service parameters; and

generating, based at least in part on the memory class of service parameters, a plurality of memory bandwidth settings to be applied to dynamically adjust priorities of memory bandwidth allocated for one or more workloads to be processed by a plurality of processor cores, wherein the generating, based at least in part on the memory class of service parameters, the plurality of memory bandwidth settings comprises determining a delay budget and setting at least one of the plurality of memory bandwidth settings to a delay value based at least in part on the delay budget and a priority of a selected memory class of service.

22. The method of claim 21 , wherein the memory class of service parameters comprise a plurality of sets of parameters, and at least one set for the selected memory class of service including one or more of: a priority, a minimum delay value, and maximum delay value, and an identifier of the selected memory class of service.

23. An apparatus comprising:

circuitry to set performance monitoring configuration parameters based at least in part on memory class of service parameters and based on proportional-integral-derivative (PID) control and to calculate an error value as a difference between a set point and a process variable of performance monitoring statistics; and

circuitry to generate memory bandwidth settings, based at least in part on the error value, for use to adjust priorities of memory bandwidth allocated for one or more workloads to be processed by a plurality of processor cores.

24. The apparatus of claim 23 , wherein the memory class of service parameters comprise a plurality of sets of parameters, and at least one set for a selected memory class of service including one or more of: a priority, a minimum delay value, and maximum delay value, and an identifier of the selected memory class of service.

25. The apparatus of claim 24 , wherein one of the memory bandwidth settings comprises a delay value based at least in part on a delay budget and the priority of the selected memory class of service.