Ultra-compact inductor made of 3D Dirac semimetal
Ultra-compact inductor devices for use in integrated circuits (e.g., RF ICs) that use 3-dimensional Dirac materials for providing the inductor. Whereas inductors currently require significant real estate on an integrated circuit, because they require use of an electrically conductive winding around an insulative core, or such metal deposited in a spiral geometry, the present devices can be far more compact, occupying significantly less space on an integrated circuit. For example, an ultra-compact inductor that could be included in an integrated circuit may include a 3-dimensional Dirac material formed into a geometric shape capable of inductance (e.g., as simple as a stripe or series of stripes of such material), deposited on a substantially non-conductive (i.e., insulative) substrate, on which the Dirac material in the selected geometric shape is positioned. Low temperature manufacturing methods compatible with CMOS manufacturing are also provided.
1. An ultra-compact inductor for use in an integrated circuit, comprising:
a 3D-DSM material formed into a geometric shape capable of inductance; and
a substantially non-conductive substrate on which the 3D-DSM material is deposited.
2. The inductor of claim 1 , wherein the 3D-DSM material is in the geometric shape of a stripe, a dot, or other closed shape.
3. The inductor of claim 1 , wherein the 3D-DSM material is in the geometric shape of a series of patterned stripes, dots, or other features separated from one another by the substantially non-conductive substrate.
4. The inductor of claim 1 , wherein the 3D-DSM material comprises at least one semimetal selected from As, B, Si, Ge, Sb, Te, Po, At, or Bi.
5. The inductor of claim 1 , wherein the 3D-DSM material comprises As.
6. The inductor of claim 1 , wherein the 3D-DSM material comprises Cd 3 As 2 .
7. The inductor of claim 1 , wherein the 3D-DSM material comprises at least one of Cd 3 As 2 , SrSi 2 , Na 3 Bi, NbAs, ZrTe 5 , MoTe 2 , or TaAs.
8. An ultra-compact inductor for use in an integrated circuit, comprising:
a 3D-DSM material formed into a geometric closed shape capable of inductance; and
a substantially non-conductive substrate on which the 3D-DSM material is deposited.
9. A method for manufacturing an ultra-compact inductor as part of an integrated circuit, the method comprising:
providing a substantially non-conductive integrated circuit substrate;
applying a polymer layer adjacent the substrate;
patterning the polymer layer, to result in a portion of the underlying substrate being exposed;
applying a 3D-DSM material over the patterned polymer layer and the substrate, the 3D-DSM material being deposited onto the substrate into locations so as to cover the previously exposed substrate;
removing the polymer layer and any 3D-DSM material applied thereover, from the substrate, so as to leave a closed geometric shape of the 3D-DSM material deposited on the substantially non-conductive substrate material, wherein the geometric shape of the 3D-DSM material is capable of inductance.
10. The method of claim 9 :
wherein patterning the polymer layer results in the polymer layer including a first polymer portion and a second polymer portion that are separated from one another by the substrate therebetween;
wherein applying the 3D-DSM material over the patterned polymer layer and the substrate results in the 3D-DSM material being deposited onto the substrate into locations between the first and second polymer portions;
wherein removing the polymer layer comprises removing the first and second polymer portions and any 3D-DSM material applied thereover, from the substrate, so that the closed geometric shape of the 3D-DSM material comprises a first closed geometric shape portion and a second closed geometric shape portion, which shape portions are separated from one another by the substantially non-conductive substrate material, wherein each geometric shape portion of the 3D-DSM material is capable of inductance.
11. The method of claim 9 , wherein the 3D-DSM material comprises Cd 3 As 2 .
12. The method of claim 9 , wherein the 3D-DSM material is applied over the patterned polymer layer at a temperature of less than about 110° C.
13. The method of claim 9 , wherein the 3D-DSM material is applied over the patterned polymer layer at a temperature of at least about 95° C.
14. The method of claim 9 , wherein the 3D-DSM material is applied over the patterned polymer layer at a temperature in a range of 95° C. to 100° C.
15. The method of claim 9 , further comprising annealing the 3D-DSM material on the substrate.
16. The method of claim 15 , wherein an annealing temperature is less than about 600° C.
17. The method of claim 15 , wherein an annealing temperature of at least about 350° C.
18. The method of claim 15 , wherein an annealing temperature in a range of 350° C. to 500° C.
19. The method of claim 9 , wherein the 3D-DSM material comprises a semimetal.
20. The method of claim 9 , wherein the 3D-DSM material comprises at least one of Cd 3 As 2 , SrSi 2 , Na 3 Bi, NbAs, ZrTe 5 , MoTe 2 , or TaAs.