Nanosheet semiconductor devices with sigma shaped inner spacer
A method of manufacturing a nanosheet field effect transistor (FET) device is provided. The method includes forming a plurality of nanosheet stacks on a substrate, the nanosheet stacks including alternating layers of sacrificial layers and active semiconductor layers. The method includes removing portions of the sacrificial layers to form angular indents in each side thereof, then filling the indents with a low-κ material layer. The method further includes forming source drain regions between the nanosheet stacks, removing remaining portions of the sacrificial layers, and then forming gate metal layers in spaces formed by the removal of the sacrificial layers.
1. A method of forming a nanosheet field effect transistor (FET) device, the method comprising:
forming a plurality of nanosheet stacks on a substrate, the nanosheet stacks including alternating layers of sacrificial layers and active semiconductor layers, wherein portions of gate metal layers have angular indents formed in each side thereof;
removing portions of the sacrificial layers to form the angular indents in each side thereof;
filling the angular indents with a low-k material layer;
forming source drain regions between the nanosheet stacks;
removing remaining portions of the sacrificial layers; and
forming the gate metal layers in spaces formed by the removal of the sacrificial layers,
wherein middle portions of the active semiconductor layer are recessed, and a thickness of the gate metal layer is greater than a thickness of the low-k material layer in the angular indents.
2. The method according to claim 1 , wherein, prior to forming the gate metal layer, the method further comprises forming a high-κ material layer in the spaced formed by removal of the sacrificial layers.
3. The method according to claim 1 , wherein the angular indents extend inward in a horizontal direction to expose portions of top and bottom surfaces of the active semiconductor layers.
4. The method according to claim 3 , wherein the low-κ material layer covers the exposed portions of the top and the bottom surfaces of the active semiconductor layers.
5. The method according to claim 1 , wherein prior to forming the gate metal layer, the method further comprises:
forming a high-κ material layer in the spaced formed by removal of the sacrificial layers.
6. The method according to claim 1 , wherein the removal of the portions of the sacrificial layers is performed along a <111> crystalline plane of the sacrificial layers.
7. The method according to claim 6 , wherein the sacrificial layers are composed of SiGe, and the active semiconductor layers are composed of Si.
8. The method according to claim 1 , wherein the gate metal layers have a first width at upper and lower portions thereof is greater than a second width at middle portions thereof.
9. A nanosheet field effect transistor (FET) device comprising:
a plurality of nanosheet stacks provided on a substrate, the nanosheet stacks including alternating layers of gate metal layers and active semiconductor layers, wherein portions of the gate metal layers have angular indents formed in each side thereof;
a low-κ material layer filling the indents in the gate metal layers; and
source drain regions provided between the nanosheet stacks,
wherein middle portions of the active semiconductor layer are recessed, and a thickness of the gate metal layer is greater than a thickness of the low-κ material layer in the angular indents.
10. The nanosheet FET device according to claim 9 , further comprising a high-κ material layer surrounding the gate metal layers, the high-κ material layer being in contact with a channel.
11. The nanosheet FET device according to claim 9 , wherein the low-κ material layer extends inward in a horizontal direction to contact portions of top and bottom surfaces of the active semiconductor layers.
12. The nanosheet FET device according to claim 9 , wherein the angular indents are triangular shaped and formed along a crystalline <111>.
13. The nanosheet FET device according to claim 9 , further comprising a high-κ material layer, where the gate metal layers surround the high-κ material layer.
14. The nanosheet FET device according to claim 9 , wherein the active semiconductor layers are composed of silicon.
15. The nanosheet FET device according to claim 9 , wherein the gate metal layers have a first width at upper and lower portions thereof is greater than a second width at middle portions thereof.
16. The nanosheet FET device according to claim 9 , wherein the source drain regions are composed of at least one of silicon, germanium, and SiGe.
17. The nanosheet FET device according to claim 9 , further comprising:
shallow trench isolation regions of the substrate formed at locations not covered by the nanosheet stacks.