Butted body contact for SOI transistor
Systems, methods, and apparatus for an improved body tie construction are described. The improved body tie construction is configured to have a lower resistance body tie exists when the transistor is “off” (Vg approximately 0 volts). When the transistor is “on” (Vg>Vt), the resistance to the body tie is much higher, reducing the loss of performance associated with presence of body tie. Space efficient Body tie constructions adapted for cascode configurations are also described.
1. A transistor device comprising:
an electrically insulating layer;
a first region having a first conductivity type;
a second region having the first conductivity type;
a conduction channel between the first region and the second region, the conduction channel having a second conductivity type;
at least one body contact region of the second conductivity type separate from the conduction channel, said body contact region fully or partially contained within the first region;
and at least one body tab of the second conductivity type in contact with the conduction channel and the at least one body contact region; and
an isolation region of the second conductivity type, the isolation region isolating the at least one body contact region from the first region,
wherein:
the first region, the second region, the conduction channel, the at least one body contact region, the at least one body tab and the isolation region are formed atop the electrically insulating layer, thereby making contact with the insulating layer.
2. The transistor device according to claim 1 , wherein the at least one body tab is configured to resistively connect the at least one body contact region to the conduction channel with a resistance value dependent on a mode of operation of the transistor device.
3. The transistor device according to claim 1 , wherein isolation of the at least one body contact region provided by the isolation region is configured to allow coupling of a potential to said body contact region that is different from a potential coupled to the first region.
4. The transistor device according to claim 1 , wherein the transistor device is a silicon-on-insulator (SOI) transistor device, fabricated using a silicon-on-insulator (SOI) technology.
5. The transistor device according to claim 4 , wherein a silicon layer of the SOI transistor device is a thin-film silicon layer.
6. The transistor device according to claim 5 , further comprising:
a first structure formed atop the conduction channel and defining a length and a width of the conduction channel;
a second structure formed atop the at least one body tab and defining a length and a width of the at least one body tab; and
a third structure formed atop the isolation region and defining a shape of the isolation region.
7. The transistor device according to claim 6 , wherein the shape of the isolation region follows a contour of the at least one body contact region in the first region.
8. The transistor device according to claim 7 , wherein:
the second structure makes contact with the first structure at one end of the second structure and with the third structure at the other end of the second structure, and,
the third structure comprises a plurality of segments arranged at the second end of the second structure, the plurality of segments defining the shape of the isolation region.
9. The transistor device according to claim 7 , wherein:
the at least one body contact region is partially contained within the first region, and
the shape of the isolation region follows an open contour.
10. The transistor device according to claim 7 , wherein:
the at least one body contact region is fully contained within the first region, and the shape of the isolation region follows a closed contour.
11. The transistor device according to claim 6 , wherein:
the second structure makes contact with the first structure at one end of the second structure and with the third structure at the other end of the second structure, and,
the third structure comprises two segments arranged on opposite sides of the second structure at the second end of the second structure, the two segments extending longitudinally along a longitudinal direction of the second structure and in an opposite direction from the first structure.
12. The transistor device according to claim 11 , wherein:
the third structure comprises additional third and fourth segments that respectively connect said two segments to the second structure.
13. The transistor device according to claim 11 , wherein:
the at least one body contact region is partially contained within the first region, and the two segments extend through the first region into a region adjacent the first region.
14. The transistor device according to claim 11 , wherein:
the at least one body contact region is fully contained within the first region, and
the third structure comprises an additional segment that joins two ends of the two segments that are away from the second end of the second structure.
15. The transistor device according to claim 6 , wherein the first structure, the second structure and the third structure form a single integral structure.
16. A field-effect transistor (FET) comprising:
a drain region having a first conductivity type;
a source region having the first conductivity type;
a gate polysilicon structure defining a body region, the body region having a second conductivity type;
at least one body contact region of the second conductivity type separate from the body region, said body contact region fully or partially contained within the source region;
at least one body tab of the second conductivity type in contact with the body region and the at least one body contact region, configured to electrically connect the at least one body contact region to the body region; and
an isolation region having the second conductivity type that isolates the at least one body contact region from one of the source and the drain region.
17. The field-effect transistor (FET) according to claim 16 , further comprising:
at least one polysilicon tab configured to define the at least one body tab; and
at least one isolation polysilicon structure configured to define the isolation region.
18. The field-effect transistor (FET) according to claim 17 , wherein the at least one polysilicon tab, the gate polysilicon structure, and the isolation polysilicon structure form a single poly silicon structure.
19. The field-effect transistor (FET) according to claim 16 , wherein
the FET is a silicon-on-insulator (SOI) FET, fabricated using a silicon-on-insulator (SOI) technology.
20. The field-effect transistor (FET) according to claim 19 , further comprising:
an insulating layer; and
a silicon layer overlying the insulating layer,
wherein the drain region, the source region, the body region, the at least one body contact region, the at least one body tab, and the isolation region are formed in the silicon layer and extend through the silicon layer to reach the insulating layer.