IP Library › Granted Patent US 11,211,454
Granted Patent B2
US 11,211,454 · App. 16/821,491 · Granted Dec 28, 2021

Semiconductor devices including source/drain regions having antimony doped layer

Inventors: Junghan Lee (Anyang-si, KR); Changhee Kim (Suwon-si, KR); Kihwan Kim (Suwon-si, KR); Suhyueon Park (Bucheon-si, KR); Jaehong Choi (Yongin-si, KR)
Assignee: Samsung Electronics Co., Ltd.
H01L29/0847H01L21/823418H01L21/823431H01L27/0886H01L29/167H01L29/42392H01L29/78696
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Quick Facts
Patent No.
US 11,211,454
App. No.
16/821,491
Granted
Dec 28, 2021
Kind
B2
Abstract

A semiconductor device including an active region protruding from an upper surface of a substrate and extending in a first horizontal direction, at least two gate electrodes extending in a second horizontal direction and crossing the active region, the second horizontal direction crossing the first horizontal direction, a source/drain region in the active region between the gate electrodes may be provided. The source/drain region includes a recess region, an outer doped layer on an inner wall of the recess region, an intermediate doped layer on the outer doped layer, and an inner doped layer on the intermediate doped layer and filling the recess region. One of the outer doped layer or the intermediate doped layer includes antimony, and the inner doped layer includes phosphorous.

Claims (23)

1. A semiconductor device comprising:

an active region protruding from an upper surface of a substrate and extending in a first horizontal direction;

at least two gate electrodes extending in a second horizontal direction and crossing the active region, the second horizontal direction crossing the first horizontal direction; and

a source/drain region in the active region between the gate electrodes,

wherein the source/drain region comprises a recess region, an outer doped layer on an inner wall of the recess region, an intermediate doped layer on the outer doped layer, and an inner doped layer on the intermediate doped layer and filling the recess region, the inner doped layer including a first portion below an upper surface of the active region and a second portion above the upper surface of the active region,

wherein one of the outer doped layer or the intermediate doped layer comprises antimony, and the inner doped layer comprises phosphorous, and

wherein the intermediate doped layer covers the first portion and is in contact with a lower surface of the second portion.

2. The semiconductor device according to claim 1 , wherein the outer doped layer comprises antimony, and the intermediate doped layer comprises arsenic.

3. The semiconductor device according to claim 2 , wherein a doping concentration of the outer doped layer is lower than a doping concentration of the intermediate doped layer.

4. The semiconductor device according to claim 3 , the doping concentration of the outer doped layer is 1×10 19 ˜2×10 20 atom/cm 3 , and the doping concentration of the intermediate doped layer is 1×10 20 ˜2×10 21 atom/cm 3 .

5. The semiconductor device according to claim 1 , wherein the outer doped layer comprises arsenic, and the intermediate doped layer comprises antimony.

6. The semiconductor device according to claim 1 , wherein the outer doped layer conformally covers the inner wall of the recess region.

7. The semiconductor device of claim 1 , wherein the outer doped layer covers a lower portion of an inner surface of the recess region, and the intermediate doped layer covers a side portion of the inner surface of the recess region and an upper surface of the outer doped layer, the side portion of the inner surface of the recess region upwardly extending from the lower portion of the inner surface of the recess region along a side of the recess region and uncovered by the outer doped layer.

8. The semiconductor device according to claim 1 , wherein the outer doped layer covers the inner wall of the recess region and has a side thickness smaller than a lower thickness.

9. The semiconductor device according to claim 8 , wherein the intermediate doped layer has a side thickness smaller than a lower thickness.

10. A semiconductor device comprising:

an active region protruding from an upper surface of a substrate and extending in a first horizontal direction;

at least two gate electrodes extending in a second horizontal direction and crossing the active region, the second horizontal direction crossing the first horizontal direction; and

a source/drain region in the active region between the gate electrodes and having a rounded lower surface, the source/drain region having an upper surface higher than an upper surface of the active region,

wherein the source/drain region comprises an inner doped layer, an intermediate doped layer surrounding a lower portion of the inner doped layer, and an outer doped layer surrounding a lower portion of the intermediate doped layer, the inner doped layer including a first portion below the upper surface of the active region and a second portion above the upper surface of the active region,

wherein the inner doped layer comprises phosphorous, the intermediate doped layer comprises arsenic, and the outer doped layer comprises antimony,

wherein a doping concentration of the outer doped layer is lower than a doping concentration of the intermediate doped layer, and

wherein the intermediate doped layer covers the first portion and is in contact with a lower surface of the second portion.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 18, 2020
From: LEE, JUNGHAN; KIM, CHANGHEE; KIM, KIHWAN; PARK, SUHYUEON; CHOI, JAEHONG
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 052146/0936 →
Priority Claims (1)
KR 10-2019-0108142 · Sep 2, 2019 · national
Continuity (1)
Related Publication 20210066455A1 · Mar 4, 2021