Semiconductor devices and methods of manufacturing semiconductor devices
In one example, a semiconductor device, comprises a first redistribution layer (RDL) substrate comprising a first dielectric structure and a first conductive structure through the first dielectric structure and comprising one or more first conductive redistribution layers, an electronic component over the first RDL substrate, wherein the electronic component is coupled with the first conductive structure, a body over a top side of the first RDL substrate, wherein the electronic component is in the body, a second RDL substrate comprising a second dielectric structure over the body, and a second conductive structure through the second dielectric structure and comprising one or more second conductive redistribution layers, and an internal interconnect coupled between the first conductive structure and the second conductive structure. Other examples and related methods are also disclosed herein.
1. A semiconductor device, comprising:
a first redistribution layer (RDL) substrate comprising:
a first dielectric structure; and
a first conductive structure through the first dielectric structure and comprising one or more first conductive redistribution layers;
an electronic component over the first RDL substrate, wherein the electronic component is coupled with the first conductive structure;
a body over a top side of the first RDL substrate, wherein the electronic component is in the body;
a second RDL substrate comprising:
a second dielectric structure over the body; and
a second conductive structure through the second dielectric structure and comprising one or more second conductive redistribution layers; and
an internal interconnect coupled between the first conductive structure and the second conductive structure;
wherein:
the first conductive structure comprises a conductive path comprising a trace and a downward via extending downward from the trace, wherein the downward via and the trace comprise a same metallic layer;
the second conductive structure comprises a conductive path comprising a trace and an upward via extending upward from the trace, wherein the upward via and the trace comprise a same metallic layer; and
the body directly contacts the first RDL substrate and directly contacts the second RDL substrate.
2. The semiconductor device of claim 1 , further comprising an underfill between the electronic component and the top side of the first RDL substrate, and contacting a bottom side of the electronic component.
3. The semiconductor device of claim 1 , wherein the body extends between a bottom side of the second RDL substrate and a top side of the electronic component.
4. The semiconductor device of claim 1 , further comprising an adhesive between the electronic component and a bottom side of the second RDL substrate, wherein the adhesive covers a top side and a lateral side of the electronic component.
5. The semiconductor device of claim 1 , wherein the first dielectric structure and the second dielectric structure are coreless.
6. The semiconductor device of claim 1 , wherein the first RDL substrate is a cavity substrate comprising the body and inner sidewalls of the body defining a cavity and bounding the electronic component.
7. The semiconductor device of claim 6 , wherein a gap is defined between one of the inner sidewalls of the body and a sidewall of the electronic component.
8. The semiconductor device of claim 1 , wherein the internal interconnect comprises a metallic-core ball having a solder coating.
9. The semiconductor device of claim 1 , wherein the internal interconnect comprises a pillar.
10. The semiconductor device of claim 1 , further comprising an additional electronic component on a bottom side of the first RDL substrate, wherein the additional electronic component is coupled with the first conductive structure and comprises a resistor, a capacitor, an inductor, or a transistor.
11. A method to manufacture a semiconductor device, comprising:
providing a bottom substrate on a bottom carrier, wherein the bottom substrate comprises a first dielectric structure, a first conductive structure, and a top interconnect at a first side of the bottom substrate;
providing an electronic component over the bottom substrate, wherein the electronic component is coupled with the first conductive structure;
providing a top substrate on a top carrier, wherein the top substrate comprises a second dielectric structure, a second conductive structure, and a bottom interconnect on a first side of the top substrate;
providing an internal interconnect coupled with one of the top interconnect of the bottom substrate or the bottom interconnect of the top substrate;
providing the top substrate over the bottom substrate, wherein the top substrate is inverted with respect to the bottom substrate;
coupling the internal interconnect to another one of the top interconnect of the bottom substrate or the bottom interconnect of the top substrate;
providing a body between the bottom substrate and the top substrate, wherein the electronic component is in the body;
removing the top carrier and the bottom carrier; and
singulating through the top substrate, the bottom substrate, and the body;
wherein the body is provided after said coupling and prior to removing the top carrier and the bottom carrier, and the body contacts the top substrate and the bottom substrate.
12. The method of claim 11 , comprising, prior to removing the top carrier:
removing the bottom carrier; and
providing an external interconnect on a bottom side of the bottom substrate and coupled with the first conductive structure.
13. The method of claim 11 , comprising providing an adhesive between a top side of the electronic component and the first side of the top substrate prior to providing the body.
14. A method to manufacture a semiconductor device, comprising:
providing a bottom substrate on a bottom carrier, wherein the bottom substrate comprises a first dielectric structure, a first conductive structure, and a top interconnect at a first side of the bottom substrate;
providing an electronic component over the bottom substrate, wherein the electronic component is coupled with the first conductive structure;
providing a top substrate on a top carrier, wherein the top substrate comprises a second dielectric structure, a second conductive structure, and a bottom interconnect on a first side of the top substrate;
providing an internal interconnect coupled with one of the top interconnect of the bottom substrate or the bottom interconnect of the top substrate;
singulating through the top substrate and the top carrier to define a first top substrate unit;
providing the first top substrate unit over the electronic component and over the bottom substrate;
coupling the internal interconnect with another one of the top interconnect of the bottom substrate or the bottom interconnect of the top substrate;
providing a body between the bottom substrate and the first top substrate unit, wherein the electronic component is in the body, and wherein the body covers a periphery of the first top substrate unit;
removing the top carrier and the bottom carrier; and
singulating the first top substrate unit, the bottom substrate, and the body;
wherein the body is provided after said coupling and prior to removing the top carrier and the bottom carrier, and the body contacts the top substrate and the bottom substrate.
15. The method of claim 14 , comprising:
prior to removing the bottom carrier,
removing the top carrier from the first top substrate unit; and
providing an additional carrier over the first top substrate unit;
after removing the bottom carrier;
providing an external interconnect on a bottom side of the bottom substrate; and
removing the additional carrier prior to performing singulating of the first top substrate unit, the bottom substrate, and the body.
16. The method of claim 14 , comprising providing an additional electronic component on a bottom side of the bottom substrate, wherein the additional electronic component is coupled with the first conductive structure.
17. The method of claim 14 , wherein:
singulating the first top substrate unit, the bottom substrate, and the body comprises:
partially sawing along the periphery of the first top substrate unit, and then singulating through the body and the bottom substrate.
18. A semiconductor device, comprising:
a first redistribution layer (RDL) substrate comprising:
a first dielectric structure; and
a first conductive structure through the first dielectric structure and comprising one or more first conductive redistribution layers;
an electronic component over the first RDL substrate, wherein the electronic component is coupled with the first conductive structure;
a body over a top side of the first RDL substrate, wherein the electronic component is in the body;
a second RDL substrate comprising:
a second dielectric structure over the body; and
a second conductive structure through the second dielectric structure and comprising one or more second conductive redistribution layers; and
an internal interconnect coupled between the first conductive structure and the second conductive structure; wherein:
the first conductive structure comprises a conductive path comprising a trace and a downward via extending downward from the trace;
the second conductive structure comprises a conductive path comprising a trace and an upward via extending upward from the trace;
the body directly contacts the first RDL substrate and directly contacts the second RDL substrate; and
the first RDL substrate is a cavity substrate comprising the body and inner sidewalls of the body defining a cavity and bounding the electronic component.
19. The semiconductor device of claim 18 , wherein a gap is defined between one of the inner sidewalls of the body and a sidewall of the electronic component.
20. The semiconductor device of claim 19 , further comprising an underfill in the gap.