Ferroelectric memory device having ferroelectric induction layer and method of manufacturing the same

1. A ferroelectric memory device comprising:

a substrate;

a channel layer over the substrate;

a first gate dielectric layer disposed on the channel layer, the first gate dielectric layer comprising a ferroelectric portion and a non-ferroelectric portion;

a ferroelectric induction layer disposed on the ferroelectric portion of the first gate dielectric layer, the ferroelectric induction layer including an insulator;

an interlayer insulation layer disposed near the ferroelectric induction layer, the interlayer insulation layer contacting the non-ferroelectric portion of the first gate dielectric layer;

a second gate dielectric layer disposed on the ferroelectric induction layer; and

a gate electrode layer disposed on the second gate dielectric layer.

2. The ferroelectric memory device of claim 1 ,

wherein the ferroelectric induction layer has a lattice constant different from a lattice constant of the first and second gate dielectric layers.

3. The ferroelectric memory device of claim 1 ,

wherein each of the first and second gate dielectric layers comprises at least one selected from the group consisting of hafnium oxide, zirconium oxide and hafnium zirconium oxide.

4. The ferroelectric memory device of claim 3 ,

wherein each of the first and second gate dielectric layers has a thickness of 5 nm to 15 nm, and

wherein the ferroelectric induction layer has a thickness of 1 nm to 5 nm.

5. The ferroelectric memory device of claim 1 ,

wherein the ferroelectric induction layer comprises crystalline magnesium oxide.

6. The ferroelectric memory device of claim 1 ,

wherein each of the first and second gate dielectric layers comprises at least one selected from the group consisting of silicon (Si), zirconium (Zr), yttrium (Y), aluminum (Al), gadolinium (Gd), strontium (Sr), and lanthanum (La) as a dopant.

7. The ferroelectric memory device of claim 1 ,

wherein the gate electrode layer has a lattice constant different from a lattice constant of the second gate dielectric layer.

8. A ferroelectric memory device comprising:

a substrate;

a gate stack disposed on the substrate, the gate stack comprising at least one gate structure and at least one interlayer insulation layer, which are alternately stacked in a direction perpendicular to the substrate;

a trench penetrating the gate stack to expose side surfaces of the gate structure and the at least one interlayer insulation layer;

a first gate dielectric layer disposed on an inner surface of the trench, the first gate dielectric layer comprising a ferroelectric portion and a non-ferroelectric portion; and

a channel layer disposed to cover the first gate dielectric layer,

wherein the gate structure comprises:

a ferroelectric induction layer in contact with the interlayer insulation layer and the first gate dielectric layer;

a second gate dielectric layer in contact with the ferroelectric induction layer; and

a gate electrode layer in contact with the second gate dielectric layer,

wherein the ferroelectric portion of the first gate dielectric layer contacts the ferroelectric induction layer, and

wherein the non-ferroelectric portion of the first gate dielectric layer contacts the interlayer insulation layer.

9. The ferroelectric memory device of claim 8 ,

wherein the ferroelectric induction layer comprises an insulator.

10. The ferroelectric memory device of claim 9 ,

wherein the ferroelectric induction layer comprises crystalline magnesium oxide.

11. The ferroelectric memory device of claim 8 ,

wherein each of the first and second gate dielectric layers comprises at least one selected from the group consisting of hafnium oxide, zirconium oxide and hafnium zirconium oxide.

12. The ferroelectric memory device of claim 8 ,

wherein the ferroelectric induction layer has a lattice constant different from a lattice constant of the first and second gate dielectric layers.

13. The ferroelectric memory device of claim 8 ,

wherein each of the first and second gate dielectric layers has a thickness of 5 nm to 15 nm in a direction perpendicular to a contact surface with the ferroelectric induction layer, and

wherein the ferroelectric induction layer has a thickness of 1 nm to 5 nm on the interlayer insulation layer and the first gate dielectric layer.

14. The ferroelectric memory device of claim 8 ,

wherein each of the first and second gate dielectric layers comprises at least one selected from the group consisting of silicon (Si), zirconium (Zr), yttrium (Y), aluminum (Al), gadolinium (Gd), strontium (Sr), and lanthanum (La) as a dopant.