Adaptive processor resource utilization
Examples herein relate to polling for input/output transactions of a network interface or a storage device, or any peripheral device. Some examples monitor clock cycles spent checking for a presence of input/output (I/O) events and processing I/O events and monitor clock cycles spent checking for presence of I/O events without completing an I/O event. Central processing unit (CPU) core utilization can be based on clock cycles spent checking for a presence of I/O events and processing I/O events and clock cycles spent checking for presence of I/O events without completion of an I/O event. For example, if core utilization is below a threshold, frequency of the core can be reduced for performing polling of I/O events. If core utilization is at or above the threshold, frequency of the core can be increased used to performing polling of I/O events.
1. A method used by a storage accelerator for managing central processing unit (CPU) core utilization based on input/output (I/O) workload, the method comprising:
based on clock cycles spent processing I/O events, selectively modifying frequency of a CPU core allocated to polling, wherein the clock cycles spent processing I/O events are based on core clock cycles spent checking for a presence of I/O events and wherein processing I/O events comprises at least one of: completed I/O events and/or uncompleted I/O events.
2. The method of claim 1 , wherein the CPU core is associated with a storage accelerator or a network interface.
3. The method of claim 1 , comprising a monitor running in user space for determining CPU core utilization based on (i) clock cycles spent checking for a presence of I/O events and processing I/O events and (ii) clock cycles spent checking for presence of I/O events without I/O completion.
4. The method of claim 3 , wherein the clock cycles spent checking for a presence of I/O events and processing I/O events comprises time stamp counter accruals for polling for work with completion of I/O events.
5. The method of claim 3 , wherein the clock cycles spent checking for presence of I/O events comprises time stamp counter accruals for polling for work without I/O transaction completions.
6. The method of claim 1 , wherein selectively modifying is performed within a network interface, storage accelerator, data center, server or rack.
7. An apparatus used by an accelerator to manage central processing unit (CPU) core utilization for input/output (I/O) polling, the apparatus comprising:
a memory device; and
at least one core communicatively coupled to the memory device, the at least one core to:
selectively modify frequency of a CPU core allocated to execute a poller based at least on clock cycles spent processing I/O events, wherein the clock cycles spent processing I/O events are based on core clock cycles spent checking for a presence of I/O events and wherein processing I/O events comprises at least one of: completed I/O events and/or uncompleted I/O events.
8. The apparatus of claim 7 , wherein the at least one core is to:
monitor for core utilization based on clock cycles spent checking for a presence of I/O events and processing I/O events.
9. The apparatus of claim 7 , wherein the at least one core is to:
monitor for core utilization based on clock cycles spent checking for presence of I/O events without I/O completion.
10. The apparatus of claim 7 , wherein a core of the at least one core is to execute a monitor to determine utilization of the CPU core allocated to execute the poller.
11. The apparatus of claim 7 , wherein the poller is to operate in user space.
12. The apparatus of claim 7 , comprising: a network interface, storage accelerator, data center, server, or rack.
13. The apparatus of claim 7 , wherein the accelerator comprises one or more of: a storage accelerator or a network interface.
14. At least one non-transitory computer-readable medium comprising instructions stored thereon, that if executed by at least one processor of a storage accelerator, cause the at least one processor to:
perform a poller and
selectively modify frequency of a CPU core that performs the poller based at least on clock cycles spent processing I/O events, wherein the clock cycles spent processing I/O events are based on core clock cycles spent checking for a presence of I/O events and wherein processing I/O events comprises at least one of: completed I/O events and/or uncompleted I/O events.
15. The at least one non-transitory computer-readable medium of claim 14 , comprising instructions stored thereon, that if executed by at least one processor, cause the at least one processor to:
monitor for core utilization based on clock cycles spent checking for a presence of I/O events and processing I/O events.
16. The at least one non-transitory computer-readable medium of claim 14 , comprising instructions stored thereon, that if executed by at least one processor, cause the at least one processor to:
monitor for core utilization based on clock cycles spent checking for presence of I/O events without I/O completion.
17. The at least one non-transitory computer-readable medium of claim 14 , comprising instructions stored thereon, that if executed by at least one processor, cause the at least one processor to:
remove a core from polling for I/O events based at least on core clock cycles spent checking for presence of I/O events without I/O completion.
18. The at least one non-transitory computer-readable medium of claim 14 , comprising instructions stored thereon, that if executed by at least one processor, cause the at least one processor to:
add a core to poll for I/O events based at least on core clock cycles spent checking for a presence of I/O events and processing I/O events.