Static random-access memory (SRAM) bit cell with channel depopulation
Embodiments disclosed herein include transistor devices with depopulated channels. In an embodiment, the transistor device comprises a source region, a drain region, and a vertical stack of semiconductor channels between the source region and the drain region. In an embodiment, the vertical stack of semiconductor channels comprises first semiconductor channels, and a second semiconductor channel over the first semiconductor channels. In an embodiment, first concentrations of a dopant in the first semiconductor channels are less than a second concentration of the dopant in the second semiconductor channel.
1. A transistor device, comprising:
a source region;
a drain region; and
a vertical stack of semiconductor channels between the source region and the drain region, wherein the vertical stack of semiconductor channels comprises:
first semiconductor channels, wherein the first semiconductor channels are active channels; and
a second semiconductor channel over the first semiconductor channels, wherein first concentrations of a dopant in the first semiconductor channels are less than a second concentration of the dopant in the second semiconductor channel, wherein the second semiconductor channel is an inactive channel.
2. The transistor device of claim 1 , wherein the second concentration of the dopant is approximately 1e19 cm −3 or greater.
3. The transistor device of claim 2 , wherein the first concentrations of the dopant are at least three orders of magnitude lower than the second concentration of the dopant.
4. The transistor device of claim 1 , wherein the transistor device is a P-type device, and wherein the dopant is an N-type dopant.
5. The transistor device of claim 4 , wherein the dopant is phosphorus or arsenic.
6. The transistor device of claim 1 , wherein the transistor device is an N-type device, and wherein the dopant is a P-type dopant.
7. The transistor device of claim 6 , wherein the dopant is boron or gallium.
8. The transistor device of claim 1 , wherein the second semiconductor channel further comprises a pre-amorphization dopant.
9. The transistor device of claim 8 , wherein the pre-amorphization dopant is germanium.
10. The transistor device of claim 1 , wherein the first semiconductor channels have a first degree of crystallinity that is higher than a second degree of crystallinity of the second semiconductor channel.
11. The transistor device of claim 1 , wherein the vertical stack of semiconductor channels further comprises a third semiconductor channel between the first semiconductor channels and the second semiconductor channel, wherein a third concentration of the dopant in the third semiconductor channel is greater than the first concentrations of the dopant in the first semiconductor channels.
12. The transistor device of claim 1 , wherein the first semiconductor channels and the second semiconductor channel are nanoribbons or nanowires.
13. A transistor device, comprising:
a source region;
a drain region; and
a vertical stack of semiconductor channels between the source region and the drain region, wherein the vertical stack of semiconductor channels comprises:
first semiconductor channels; and
a second semiconductor channel over the first semiconductor channels, wherein first concentrations of a dopant in the first semiconductor channels are less than a second concentration of the dopant in the second semiconductor channel, wherein the first semiconductor channels have a first degree of crystallinity that is higher than a second degree of crystallinity of the second semiconductor channel.
14. A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a source region;
a drain region; and
a vertical stack of semiconductor channels between the source region and the drain region, wherein the vertical stack of semiconductor channels comprises:
first semiconductor channels, wherein the first semiconductor channels are active channels; and
a second semiconductor channel over the first semiconductor channels, wherein first concentrations of a dopant in the first semiconductor channels are less than a second concentration of the dopant in the second semiconductor channel, wherein the second semiconductor channels are inactive channels.
15. The computing device of claim 14 , further comprising:
a memory coupled to the board.
16. The computing device of claim 14 , further comprising:
a communication chip coupled to the board.
17. The computing device of claim 14 , further comprising:
a battery coupled to the board.
18. The computing device of claim 14 , wherein the component is a packaged integrated circuit die.