Dual damascene fully aligned via in interconnects
Dual damascene interconnect structures with fully aligned via integration schemes are formed using different dielectric materials having different physical properties. A low-k dielectric material having good fill capabilities fills nanoscopic trenches in such structures. Another dielectric material forms the remainder of the dielectric portion of the interconnect layer and has good reliability properties, though not necessarily good trench filling capability. The nanoscopic trenches may be filled with a flowable polymer using flowable chemical vapor deposition. A further dielectric layer having good reliability properties is deposited over the metal lines and dual damascene patterned to form interconnect line and via patterns. The patterned dielectric layer is filled with interconnect metal, thereby forming interconnect lines and fully aligned via conductors. The via conductors are electrically connected to previously formed metal lines below.
1. A method of forming an interconnect layer over a semiconductor substrate, comprising:
obtaining a bottom structure including:
a first dielectric layer comprising a first low-k dielectric material above the semiconductor substrate; and
metal lines within the first dielectric layer;
recessing the metal lines, thereby forming open-ended trenches within the first dielectric layer and directly above the metal lines;
depositing a conformal cap/etch stop layer over the first dielectric layer and the metal lines;
filling the open-ended trenches with a second low-k dielectric material, the second low-k dielectric material and the first low-k dielectric material having one or more different physical properties, wherein filling the open-ended trenches with the second low-k dielectric material comprises depositing a second dielectric layer over the conformal cap/etch stop layer;
depositing a top dielectric layer over the bottom structure;
patterning the top dielectric layer, thereby forming one or more top trenches within the top dielectric layer and one or more vias extending downwardly from each of the one or more top trenches, the one or more vias being vertically aligned with one or more portions of the open-ended trenches;
removing the second low-k dielectric material from the one or more portions of the open-ended trenches vertically aligned with the one or more vias; and
depositing interconnect metal within the one or more top trenches, the one or more vias, and the one or more portions of the open-ended trenches, the interconnect metal within the one or more vias being electrically connected to one or more of the metal lines.
2. The method of claim 1 , further including:
removing portions of the conformal cap/etch stop layer over the metal lines following removing the second low-k dielectric material from the portions of the one or more of the open-ended trenches.
3. The method of claim 2 , wherein the second low-k dielectric material is flowable during filling the open-ended trenches and depositing the second dielectric layer comprises flowing the second low-k dielectric material into the open-ended trenches.
4. The method of claim 3 , wherein the open-ended trenches each have an average width of fifty nanometers or less.
5. The method of claim 4 , wherein the one or more physical properties comprises time dependent dielectric breakdown (TDDB), and further wherein first low-k dielectric material has superior time dependent dielectric breakdown (TDDB) properties than the second low-k dielectric material.
6. The method of claim 5 , wherein filling the open-ended trenches comprises spin coating the second low-k dielectric material.
7. The method of claim 6 , wherein obtaining the bottom structure comprises depositing the first low-k dielectric material over the substrate using chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), or radio-frequency CVD (RFCVD).
8. The method of claim 5 , wherein filling the open-ended trenches comprises depositing the second low-k dielectric material using flowable chemical vapor deposition.
9. The method of claim 8 , wherein obtaining the bottom structure comprises depositing the first low-k dielectric material over the substrate using chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), or radio-frequency CVD (RFCVD).
10. A method of fabricating an interconnect layer, comprising:
recessing a plurality of metal lines within a first dielectric layer comprising a first low-k dielectric material, thereby forming recessed metal lines and a plurality of open-ended trenches extending, respectively, within the first dielectric layer above the metal lines;
conformally depositing a dielectric cap/etch stop layer over the first dielectric layer and the recessed metal lines;
flowing a second low-k dielectric material over the dielectric cap/etch stop layer, thereby forming a second dielectric layer filling the open-ended trenches, the second low-k dielectric material being a flowable dielectric, the second low-k dielectric material and the first low-k dielectric material having one or more different physical properties;
planarizing the second dielectric layer, thereby removing the second dielectric material above the open-ended trenches;
depositing a third dielectric layer over the second dielectric layer and the cap/etch stop layer;
dual damascene patterning the third dielectric layer, thereby forming one or more top trenches and vias extending downwardly from the one or more top trenches;
removing portions of the second dielectric layer beneath the vias;
removing one or more portions of the dielectric cap/etch stop layer beneath the vias; and
depositing interconnect metal within the one or more top trenches, the vias, and one or more of the open-ended trenches, the interconnect metal being electrically connected to one or more of the recessed metal lines.
11. The method of claim 10 , wherein the first low-k dielectric material and the second low-k dielectric material have different chemical compositions.
12. The method of claim 10 , wherein the one or more different physical properties comprises time dependent dielectric breakdown (TDDB), the first low-k dielectric material having superior time dependent dielectric breakdown (TDDB) properties than the second low-k dieelectric material.
13. The method of claim 12 , wherein the third dielectric layer comprises a third low-k dielectric material having superior time dependent dielectric breakdown (TDDB) properties than the second low-k dielectric material.
14. A method of forming an interconnect layer over a semiconductor substrate, comprising:
obtaining a bottom structure including:
a first dielectric layer comprising a first low-k dielectric material above the semiconductor substrate; and
metal lines within the first dielectric layer;
recessing the metal lines, thereby forming open-ended trenches within the first dielectric layer and directly above the metal lines;
flowing a second low-k dielectric material into the open-ended trenches, the second low-k dielectric material and the first low-k dielectric material having one or more different physical properties;
planarizing the second low-k dielectric material;
depositing a top dielectric layer over the bottom structure, the top dielectric layer and the second low-k dielectric material in the open-ended trenches having one or more different physical properties;
patterning the top dielectric layer, thereby forming one or more top trenches within the top dielectric layer and one or more vias extending downwardly from each of the one or more top trenches, the one or more vias being vertically aligned with one or more portions of the open-ended trenches;
removing the second low-k dielectric material from the one or more portions of the open-ended trenches vertically aligned with the one or more vias; and
depositing interconnect metal within the one or more top trenches, the one or more vias, and the one or more portions of the open-ended trenches, the interconnect metal within the one or more vias being electrically connected to one or more of the metal lines.