IP Library › Granted Patent US 12,176,268
Granted Patent B2
US 12,176,268 · App. 16/828,405 · Granted Dec 24, 2024

Open cavity bridge co-planar placement architectures and processes

Inventors: Omkar Karhade (Chandler, AZ); Digvijay Raorane (Chandler, AZ); Sairam Agraharam (Chandler, AZ); Nitin Deshpande (Chandler, AZ); Mitul Modi (Phoenix, AZ); Manish Dubey (Chandler, AZ); Edvin Cetegen (Chandler, AZ)
Assignee: Intel Corporation
H01L23/4821H01L23/49503H01L23/5381
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Quick Facts
Patent No.
US 12,176,268
App. No.
16/828,405
Granted
Dec 24, 2024
Kind
B2
Abstract

Embodiments disclosed herein include multi-die packages with open cavity bridges. In an example, an electronic apparatus includes a package substrate having alternating metallization layers and dielectric layers. The package substrate includes a first plurality of substrate pads and a second plurality of substrate pads. The package substrate also includes an open cavity between the first plurality of substrate pads and the second plurality of substrate pads, the open cavity having a bottom and sides. The electronic apparatus also includes a bridge die in the open cavity, the bridge die including a first plurality of bridge pads, a second plurality of bridge pads, and conductive traces. An adhesive layer couples the bridge die to the bottom of the open cavity. A gap is laterally between the bridge die and the sides of the open cavity, the gap surrounding the bridge die.

Claims (15)

1. An electronic apparatus, comprising:

a package substrate having alternating metallization layers and dielectric layers, the package substrate comprising:

a first plurality of substrate pads and a second plurality of substrate pads;

an open cavity between the first plurality of substrate pads and the second plurality of substrate pads, the open cavity having a bottom and sides; and a plurality of conductive vias directly coupling the metallization layers and the substrate pads; and

a bridge die in the open cavity, the bridge die comprising a first plurality of bridge pads, a second plurality of bridge pads, and conductive traces;

an adhesive layer coupling the bridge die to the bottom of the open cavity, the adhesive layer beneath and extending laterally beyond outermost sides of the bridge die; and

a gap laterally between the bridge die and the sides of the open cavity, the gap surrounding the bridge die.

2. The electronic apparatus of claim 1 , further comprising:

a first die coupled to the first plurality of substrate pads and the first plurality of bridge pads; and

a second die coupled to the second plurality of substrate pads and the second plurality of bridge pads, the second die coupled to the first die by the conductive traces of the bridge die.

3. The electronic apparatus of claim 2 , wherein the first die is coupled to the first plurality of substrate pads and the first plurality of bridge pads by a first plurality of solder structures, and the second die is coupled to the second plurality of substrate pads and the second plurality of bridge pads by a second plurality of solder structures.

4. The electronic apparatus of claim 2 , further comprising:

a board coupled to a side of the package substrate opposite the first die and the second die.

5. The electronic apparatus of claim 1 , wherein adjacent pads of the first plurality of bridge pads and adjacent pads of the second plurality of bridge pads have a first pitch, and wherein adjacent pads of the first plurality of substrate pads and adjacent pads of the second plurality of substrate pads have a second pitch greater than the first pitch.

6. The electronic apparatus of claim 5 , wherein the first pitch is less than approximately 100 μm and the second pitch is greater than approximately 100 μm.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 11, 2020
From: KARHADE, OMKAR; RAORANE, DIGVIJAY; AGRAHARAM, SAIRAM; DESHPANDE, NITIN; MODI, MITUL; DUBEY, MANISH; CETEGEN, EDVIN
To: INTEL CORPORATION
Reel/Frame 054340/0198 →
Continuity (1)
Related Publication 20210305132A1 · Sep 30, 2021