Transistor and logic gate
A transistor includes a substrate having a plurality of source/drain regions and a channel region between the source/drain regions, a gate, and a gate dielectric layer between the gate and the substrate. The substrate tapers in a direction away from the gate dielectric layer in top view. The gate is embedded in the gate dielectric layer. The transistor structure density can be improved.
1. A transistor, comprising:
a substrate having a plurality of source/drain regions and a channel region between the source/drain regions;
a gate; and
a gate dielectric layer between the gate and the substrate, wherein the substrate tapers in a direction away from the gate dielectric layer in top view, and wherein the gate is embedded in the gate dielectric layer.
2. The transistor of claim 1 , wherein the gate dielectric layer, the substrate and the gate form a semi-elliptical profile in top view.
3. The transistor of claim 1 , wherein the gate dielectric layer is embedded in the substrate.
4. The transistor of claim 1 , wherein the gate comprises a convex surface interfaced with the gate dielectric layer.
5. The transistor of claim 1 , wherein the substrate comprises a concave surface interfaced with the gate dielectric layer.
6. The transistor of claim 1 , wherein the gate and the substrate respectively comprise a convex surface and a concave surface, and the gate dielectric layer is between the convex surface and the concave surface.
7. The transistor of claim 1 , further comprising:
a first isolation layer in which the substrate is embedded, wherein the first isolation layer has a serpentine shape in top view.
8. The transistor of claim 7 , further comprising:
a second isolation layer, wherein the gate is between the second isolation layer and the gate dielectric layer, and the second isolation layer has a different shape from the first isolation layer in top view.
9. The transistor of claim 8 , wherein the second isolation layer has a stripe shape in top view.
10. The transistor of claim 1 , wherein the substrate tapers to a point.
11. A logic gate, comprising:
a first sub-layer comprising a first conductive connection element;
a second sub-layer over the first sub-layer, wherein the second sub-layer comprising a first via vertically connected to the first conductive connection element;
a third sub-layer over the second sub-layer and comprising a transistor region and a second conductive connection element horizontally connected to the transistor region, wherein the first via is vertically connected to the transistor region, and the transistor region comprises a plurality transistors of claim 1 ;
a fourth sub-layer comprising a second via vertically connected to the third sub-layer;
a fifth sub-layer over the fourth sub-layer and comprising a third conductive connection element, wherein the second via is vertically connected to the third conductive connection element; and
a through-silicon via vertically connected to the third conductive connection element.
12. The logic gate of claim 11 , wherein the first sub-layer, the second sub-layer, the third sub-layer, the fourth sub-layer, the fifth sub-layer, and the through-silicon via are stacked in sequence.
13. The logic gate of claim 11 , wherein the third sub-layer further comprises an input terminal that is horizontally connected to the second conductive connection element.
14. The logic gate of claim 13 , wherein the transistors comprise a PMOS transistor and a NMOS transistor, a gate of the PMOS transistor is electrically connected to a gate of the NMOS transistor through the second conductive connection element, wherein the gate of the PMOS transistor and the gate of the NMOS transistor are as inputs.
15. The logic gate of claim 14 , wherein the first sub-layer comprises an output terminal horizontally connected to the first conductive connection element, wherein a drain region of the PMOS transistor and a drain region of the NMOS transistor are as outputs.
16. The logic gate of claim 13 , wherein the transistors comprise at least two PMOS transistors and at least two NMOS transistors, and wherein the PMOS transistors are electrically connected in parallel and the NMOS transistors are electrically connected in series.
17. The logic gate of claim 16 , wherein the first sub-layer comprises an output terminal horizontally connected to the first conductive connection element.
18. The logic gate of claim 13 , wherein the transistors comprise at least two PMOS transistors and at least two NMOS transistors, and wherein the PMOS transistors are electrically connected in series and the NMOS transistors are electrically connected in parallel.
19. The logic gate of claim 18 , wherein the fifth sub-layer comprises an output terminal horizontally connected to the third conductive connection element.
20. The logic gate of claim 11 , wherein the transistors of the third sub-layer comprise a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor,
wherein the first transistor and the second transistor define a first inverter, the third transistor and the fourth transistor define a second inverter, and the first inverter is electrically cross-coupled to the second inverter,
wherein the first inverter and the second inverter electrically connected to the sixth transistor and the fifth transistor through the first sub-layer and the second sub-layer, respectively.