Processor authentication method
View Patent ↗The disclosure includes a method of authenticating a processor that includes an arithmetic and logic unit. At least one decoded operand of at least a portion of a to-be-executed opcode is received on a first terminal of the arithmetic and logic unit. A signed instruction is received on a second terminal of the arithmetic and logic unit. The signed instruction combines a decoded instruction of the to-be-executed opcode and at least one previously-executed opcode.
1. A method, comprising:
decoding a first opcode into a decoded instruction and a plurality of decoded operands;
receiving, on a first terminal of an arithmetic and logic unit, a first decoded operand of the plurality of decoded operands;
generating a first instruction by combining the decoded instruction with a data corresponding to a second opcode; and
receiving, on a second terminal of the arithmetic and logic unit, the first instruction,
wherein the second opcode is an opcode that has been executed by the arithmetic and logic unit before the first opcode.
2. The method of claim 1 , wherein the first instruction is generated at a combination circuit.
3. The method of claim 2 , wherein the combination circuit receives as an input the decoded instruction of the first opcode and the data corresponding to the second opcode.
4. The method of claim 1 , wherein the second opcode is stored on a context register bank.
5. The method of claim 1 , comprising calculating a result by processing, at the arithmetic and logic unit, the first instruction with respect to the first decoded operand.
6. The method of claim 1 , wherein the generating the first instruction combines the decoded instruction of the first opcode, at least a part of the second opcode, and a previous calculation result of the arithmetic and logic unit.
7. A processor, comprising:
a combination circuit that operates to generate a first instruction by combining a second instruction of a first opcode with a signature data corresponding to a second opcode; and
an arithmetic and logic unit having a first terminal and a second terminal, the first terminal being configured to receive a first operand of at least a portion of the first opcode and the second terminal being configured to receive the first instruction
wherein the second opcode is an opcode that has been executed by the arithmetic and logic unit prior to the first opcode.
8. The processor of claim 7 , wherein the combination circuit is configured to be controlled by an operand of the first opcode.
9. The processor of claim 7 , comprising a context register bank configured to store one or more of the second opcode or an execution result of the arithmetic and logic unit.
10. The processor of claim 7 , wherein the arithmetic and logic unit is configured to process the first instruction received on its first terminal and the at least one operand received on its second terminal.
11. The processor of claim 7 , wherein the signature data is one or more of at least a part of the second opcode or an execution result of the second opcode.
12. The processor of claim 7 , comprising a decoding circuit configured to decode the first opcode into a plurality of operands including the first operand and the second instruction.
13. The processor of claim 12 , comprising a multiplexer configured to receive the plurality of operands and to deliver the first operand to the first terminal of the arithmetic and logic unit.
14. An integrated circuit, comprising:
a decoding circuitry that operates to decode a first opcode into a decoded instruction and a plurality of decoded operands;
a multiplexer circuitry that operates to select a first decoded operand from the plurality of decoded operands;
a combination circuitry that operates to generate a signed instruction by combining the decoded instruction and a signature data corresponding to a second opcode that is decoded by the decoding circuitry before the first opcode; and
an arithmetic and logic circuitry that operates to calculate a first result based on the first decoded operand and the signed instruction.
15. The integrated circuit of claim 14 , wherein the multiplexer operates to deliver a second decoded operand of the plurality of decoded operands to the combination circuitry, the second decoded operand controlling the combination circuitry in generating the signed instruction.
16. The integrated circuit of claim 14 , comprising a register bank circuitry that operates to store the second opcode.
17. The integrated circuit of claim 14 , wherein the signature data is a part of the second opcode.
18. The integrated circuit of claim 14 , wherein the signature data includes the second opcode in its entirety.
19. The integrated circuit of claim 14 , wherein the signature data is an execution result of the second opcode.
20. The integrated circuit of claim 14 , comprising a context register circuitry configured to store one or more of the second opcode or an execution result of the arithmetic and logic circuitry.