Gate-all-around integrated circuit structures having insulator fin on insulator substrate
Gate-all-around integrated circuit structures having an insulator fin on an insulator substrate, and methods of fabricating gate-all-around integrated circuit structures having an insulator fin on an insulator substrate, are described. For example, an integrated circuit structure includes an insulator fin on an insulator substrate. A vertical arrangement of horizontal semiconductor nanowires is over the insulator fin. A gate stack surrounds a channel region of the vertical arrangement of horizontal semiconductor nanowires, and the gate stack is overlying the insulator fin. A pair of epitaxial source or drain structures is at first and second ends of the vertical arrangement of horizontal semiconductor nanowires and at first and second ends of the insulator fin.
1. An integrated circuit structure, comprising:
an insulator fin directly on an insulator layer of an insulator substrate;
a vertical arrangement of horizontal semiconductor nanowires over the insulator fin;
a gate stack surrounding a channel region of the vertical arrangement of horizontal semiconductor nanowires, and the gate stack overlying the insulator fin; and
a pair of epitaxial source or drain structures at first and second ends of the vertical arrangement of horizontal semiconductor nanowires and laterally adjacent to and in contact with first and second ends of the insulator fin.
2. The integrated circuit structure of claim 1 , wherein the insulator fin has a vertical thickness approximately the same as a vertical thickness of each of the nanowires of the vertical arrangement of horizontal semiconductor nanowires.
3. The integrated circuit structure of claim 1 , wherein the insulator fin has a vertical thickness greater than a vertical thickness of each of the nanowires of the vertical arrangement of horizontal semiconductor nanowires.
4. The integrated circuit structure of claim 1 , wherein the insulator fin has a vertical thickness less than a vertical thickness of each of the nanowires of the vertical arrangement of horizontal semiconductor nanowires.
5. The integrated circuit structure of claim 1 , wherein the insulator fin comprises silicon oxide, and the vertical arrangement of horizontal semiconductor nanowires comprises silicon.
6. The integrated circuit structure of claim 1 , wherein the vertical arrangement of horizontal semiconductor nanowires comprises silicon germanium or a group III-V material.
7. The integrated circuit structure of claim 1 , wherein the insulator substrate comprises a layer of silicon oxide, and the insulator fin is on the layer of silicon oxide.
8. The integrated circuit structure of claim 1 , wherein the insulator substrate comprises a layer of silicon nitride, and the insulator fin is on the layer of silicon nitride.
9. The integrated circuit structure of claim 1 , wherein a bottom of the pair of epitaxial source or drain structures is on the insulator substrate.
10. The integrated circuit structure of claim 9 , wherein the bottom of the pair of epitaxial source or drain structures is co-planar with a bottom of the insulator fin.
11. The integrated circuit structure of claim 1 , wherein the insulator substrate comprises a remnant catalyst material beneath the insulator fin.
12. The integrated circuit structure of claim 1 , wherein the pair of epitaxial source or drain structures is a pair of non-discrete epitaxial source or drain structures.
13. The integrated circuit structure of claim 1 , wherein the gate stack comprises a high-k gate dielectric layer and a metal gate electrode.
14. A method of fabricating an integrated circuit structure, the method comprising:
forming a vertical arrangement of horizontal semiconductor nanowires above a semiconductor fin above an insulator substrate;
forming a dummy gate stack surrounding a channel region of the vertical arrangement of horizontal semiconductor nanowires, the dummy gate stack overlying the semiconductor fin;
forming a pair of epitaxial source or drain structures at first and second ends of the vertical arrangement of horizontal semiconductor nanowires and laterally adjacent to first and second ends of the semiconductor fin;
removing the dummy gate stack;
oxidizing the semiconductor fin to form an insulator fin, the insulator fin directly on an insulator layer of the insulator substrate; and
forming a permanent gate stack surrounding the channel region of the vertical arrangement of horizontal semiconductor nanowires, the permanent gate stack overlying the insulator fin.
15. The method of claim 14 , wherein forming the pair of epitaxial source or drain structures comprises forming a non-discrete pair of epitaxial source or drain structures.
16. A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
an insulator fin directly on an insulator layer of an insulator substrate;
a vertical arrangement of horizontal semiconductor nanowires over the insulator fin;
a gate stack surrounding a channel region of the vertical arrangement of horizontal semiconductor nanowires, and the gate stack overlying the insulator fin; and
a pair of epitaxial source or drain structures at first and second ends of the vertical arrangement of horizontal semiconductor nanowires and laterally adjacent to and in contact with first and second ends of the insulator fin.
17. The computing device of claim 16 , further comprising:
a memory coupled to the board.
18. The computing device of claim 16 , further comprising:
a communication chip coupled to the board.
19. The computing device of claim 16 , wherein the component is a packaged integrated circuit die.
20. The computing device of claim 16 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.