Convolutional network hardware accelerator device, system and method
A Multiple Accumulate (MAC) hardware accelerator includes a plurality of multipliers. The plurality of multipliers multiply a digit-serial input having a plurality of digits by a parallel input having a plurality of bits by sequentially multiplying individual digits of the digit-serial input by the plurality of bits of the parallel input. A result is generated based on the multiplication of the digit-serial input by the parallel input. An accelerator framework may include multiple MAC hardware accelerators, and may be used to implement a convolutional neural network. The MAC hardware accelerators may multiple an input weight by an input feature by sequentially multiplying individual digits of the input weight by the input feature.
1. A system, comprising:
an addressable memory array;
one or more processing cores; and
an accelerator framework including a plurality of Multiply ACcumulate (MAC) hardware accelerators, wherein a MAC hardware accelerator of the plurality of MAC hardware accelerators, in operation, multiplies an input weight having a plurality of digits by an input feature by sequentially multiplying individual digits of the plurality of digits of the input weight by the input feature, wherein the system comprises pre-processing logic, which, in operation, controls gating of multipliers of the MAC hardware accelerators.
2. The system of claim 1 , comprising pre-processing logic that, in operation, controls gating of multipliers of the MAC hardware accelerators.
3. The system of claim 1 , wherein the pre-processing logic includes passive selection logic within one or more gating circuits.
4. The system of claim 3 , wherein a gating circuit of the one or more gating circuits includes an OR gate, a flip-flop, and an AND gate that are serially coupled to control a clock of a digit-serial multiplier unit within one of the MAC hardware accelerators.
5. The system of claim 1 , wherein the controlling the gating of a multiplier of a MAC hardware accelerator of the plurality of MAC hardware accelerators comprises:
detecting zero-value digits of weight inputs to the multiplier; and
gating the multiplier of the MAC hardware accelerator in response to detection of a zero-value digit weight input to the multiplier.
6. The system of claim 1 , wherein the individual digits of the input weight are stored in a sign and magnitude coding format.
7. A system, comprising:
an addressable memory array;
one or more processing cores; and
an accelerator framework including a plurality of Multiply ACcumulate (MAC) hardware accelerators, wherein a MAC hardware accelerator of the plurality of MAC hardware accelerators, in operation, multiplies an input weight having a plurality of digits by an input feature by sequentially multiplying individual digits of the plurality of digits of the input weight by the input feature, wherein a MAC hardware accelerator of the plurality of MAC hardware accelerators has a number P of digit-serial multipliers, and, in operation, the P digit-serial multipliers produce one W-bit by W-bit multiplication result in a clock cycle, wherein W and P are integers greater than 1.
8. The system of claim 7 , wherein the MAC hardware accelerator comprises accumulation circuitry and timing control circuitry, and the timing control circuitry, in operation, controls data flow between the P digit-serial multipliers and the accumulation circuitry of the MAC hardware accelerator.
9. The system of claim 8 , wherein the accelerator framework, in operation, controls data flow to the plurality of MAC hardware accelerators to synchronize operation of the plurality of MAC hardware accelerators.
10. A system, comprising:
an addressable memory array;
one or more processing cores; and
an accelerator framework including a plurality of Multiply ACcumulate (MAC) hardware accelerators, wherein a MAC hardware accelerator of the plurality of MAC hardware accelerators, in operation, multiplies an input weight having a plurality of digits by an input feature by sequentially multiplying individual digits of the plurality of digits of the input weight by the input feature, wherein the MAC hardware accelerators, in operation, perform one or more multiplication operations via sign-magnitude coding.
11. The system of claim 10 , wherein the MAC hardware accelerators, in operation, convert an output of at least one multiplication operation of the one or more multiplication operations to 2's complement prior to an accumulation step associated with the at least one multiplication operation.
12. A system, comprising:
an addressable memory array;
one or more processing cores; and
an accelerator framework including a plurality of Multiply ACcumulate (MAC) hardware accelerators, wherein a MAC hardware accelerator of the plurality of MAC hardware accelerators, in operation, multiplies an input weight having a plurality of digits by an input feature by sequentially multiplying individual digits of the plurality of digits of the input weight by the input feature, wherein the individual digits of the input weight are stored in a series of words of the memory array.
13. The system of claim 12 , wherein a word in the series of words stores digits of a plurality of different input weights.
14. A mobile computing device, comprising:
an imaging sensor that captures images; and
processing circuitry, which, in operation, implements a deep convolutional neural network, the processing circuitry including:
a memory; and
an accelerator framework coupled to the memory, the accelerator framework including a plurality of Multiply ACcumulate (MAC) hardware accelerators, which, in operation, multiply an input weight having a plurality of digits by an input feature by sequentially multiplying individual digits of the plurality of digits of the input weight by the input feature.
15. The mobile computing device of claim 14 , comprising pre-processing logic, which, in operation, controls gating of multipliers of the MAC hardware accelerators.
16. The mobile computing device of claim 15 , wherein the controlling the gating of a multiplier of a MAC hardware accelerator of the plurality of MAC hardware accelerators comprises:
detecting zero-value digits of weight inputs to the multiplier; and
gating the multiplier of the MAC hardware accelerator in response to detection of a zero-value digit weight input to the multiplier.
17. The mobile computing device of claim 14 , wherein a MAC hardware accelerator of the plurality of MAC hardware accelerators has a number P of digit-serial multipliers, and, in operation, the P digit-serial multipliers produce one W-bit by W-bit multiplication result in a clock cycle, wherein W and P are integers greater than 1.
18. The mobile computing device of claim 14 , wherein the individual digits of the input weight are stored in a series of words of the memory.
19. A method, comprising:
performing a plurality of multiply accumulate operations using a plurality of Multiply ACcumulate (MAC) hardware accelerators of an accelerator framework, wherein the MAC hardware accelerators multiply a digit-serial input having a plurality of digits by a parallel input having a plurality of bits by sequentially multiplying individual digits of the digit-serial input by the plurality of bits of the parallel input; and
generating an output based on results of the plurality of multiple accumulate operations, wherein the performing the plurality of multiple accumulate operations includes controlling gating of multipliers of the MAC hardware accelerators using pre-processing logic of the accelerator framework.
20. The method of claim 19 , comprising:
gating a multiplier of a MAC hardware accelerator of the plurality of MAC hardware accelerators in response to detecting a zero-value input digit to the multiplier.
21. The method of claim 19 , comprising:
storing the individual digits of the digit-serial input in a series of words of a memory.
22. The method of claim 21 , wherein a word in the series of words stores digits of a plurality of different digit-serial inputs.
23. A Multiple Accumulate (MAC) hardware accelerator, comprising:
a plurality of multipliers, which, in operation, multiply a digit-serial input having a plurality of digits by a parallel input having a plurality of bits by sequentially multiplying individual digits of the digit-serial input by the plurality of bits of the parallel input; and
circuitry coupled to the plurality of multipliers, wherein the circuitry, in operation, outputs a result based on the multiplication of the digit-serial input by the parallel input.
24. The MAC hardware accelerator of claim 23 , comprising pre-processing logic that, in operation, controls gating of the plurality of multipliers.
25. The MAC hardware accelerator of claim 24 , wherein the pre-processing logic includes an OR gate, a flip-flop, and an AND gate that are serially coupled to control a clock of a multiplier of the plurality of multipliers.
26. The MAC hardware accelerator of claim 24 , wherein the pre-processing logic, in operation:
detects zero-value digits input to a multiplier of the plurality of multipliers; and
gates the multiplier in response to detection of a zero-value digit input to the multiplier.
27. The MAC hardware accelerator of claim 23 , wherein the plurality of multipliers produce one W-bit by W-bit multiplication result in a clock cycle, wherein W is an integer greater than 1.
28. The MAC hardware accelerator of claim 27 , wherein the MAC hardware accelerator comprises accumulation circuitry and timing control circuitry, and the timing control circuitry, in operation, controls data flow between the P digit-serial multipliers and the accumulation circuitry of the MAC hardware accelerator.